[M] Change in coreboot[main]: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP

[Patrick Rudolph (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu.

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81098?usp=email )

Change subject: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP
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Patch Set 2:

(3 comments)

File src/soc/intel/xeon_sp/chip_common.c:

https://review.coreboot.org/c/coreboot/+/81098/comment/d3287f54_d2b83609 :
PS2, Line 170: northbridge_write_acpi_tables
Can this be merged into iio_pcie_domain_ops? You could check in northbridge_write_acpi_tables() if the dev->path is domain 0 and return if not. That would result in even less code.

https://review.coreboot.org/c/coreboot/+/81098/comment/57c0925a_602393b6 :
PS2, Line 198: domain
maybe you can set .bus, .stack and .socket here from the passed arguments to drop the lines above. That would make it easier to read.
Technically it would be the same, but you get rid of the new union.

https://review.coreboot.org/c/coreboot/+/81098/comment/274aaa77_049a9f7b :
PS2, Line 287: downstream
dev->path.domain.domain == 0