Attention is currently required from: Werner Zeh. Uwe Poeche has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63547 )
Change subject: soc/intel/elkhartlake/systemagent: Disable RAPL based on Kconfig ......................................................................
Patch Set 6:
(7 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63547/comment/2c436583_a76c1bd4 PS2, Line 7: soc/intel/elkhartlake/systemagent: possibility of deactivate RAPL
soc/intel/elkhartlake: Disable RAPL based on Kconfig
Done
https://review.coreboot.org/c/coreboot/+/63547/comment/1347ec41_51e98d9a PS2, Line 9: deactivate
disable
Done
https://review.coreboot.org/c/coreboot/+/63547/comment/47c15a4a_18303a15 PS2, Line 10: as in APL based boards
SOC_INTEL_DISABLE_POWER_LIMITS
Done
https://review.coreboot.org/c/coreboot/+/63547/comment/ca56c2d9_16198939 PS2, Line 10: The only : difference in EHL is the necessary usage of an MCHBAR register instead : the relevant MSR (Intel changes EDS at the moment).
Other than on previouse SOCs this needs to be done in an MCHBAR mapped register rather than via MSR […]
Done
https://review.coreboot.org/c/coreboot/+/63547/comment/5452dc6a_9cb84495 PS2, Line 15: On siemens/mc_ehl1 checking the MCHBAR register with and without the : relevant config switch.
Check MCHBAR mapped registers (MCH_PKG_POWER_LIMIT) on mc_ehl1.
Done
File src/soc/intel/elkhartlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/63547/comment/e3da2248_71789467 PS2, Line 51: u32
elkhartlake code usually uses uint{8,16,32}_t types. I would do it here, too to stay consistent.
Done
https://review.coreboot.org/c/coreboot/+/63547/comment/3db96762_b0016772 PS2, Line 61: Skip setting RAPL per configuration\n
Here you actually disable RAPL directly, so maybe "Disable RAPL" would be more clear here?
Done