Change in coreboot[master]: soc/intel/broadwell: Use southbridge common RCBA

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50041 )

Change subject: soc/intel/broadwell: Use southbridge common RCBA
......................................................................

soc/intel/broadwell: Use southbridge common RCBA

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I94953bed3f331848271464bee829f8209167f150
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50041
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/soc/intel/broadwell/acpi/hostbridge.asl
M src/soc/intel/broadwell/include/soc/iomap.h
M src/soc/intel/broadwell/include/soc/rcba.h
M src/soc/intel/broadwell/pch/acpi/pch.asl
M src/soc/intel/broadwell/pch/bootblock.c
M src/soc/intel/broadwell/pch/lpc.c
6 files changed, 8 insertions(+), 22 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/soc/intel/broadwell/acpi/hostbridge.asl b/src/soc/intel/broadwell/acpi/hostbridge.asl
index e36fa47..3ba5046 100644
--- a/src/soc/intel/broadwell/acpi/hostbridge.asl
+++ b/src/soc/intel/broadwell/acpi/hostbridge.asl
@@ -174,7 +174,7 @@
    Name (_UID, 1)

Name (PDRS, ResourceTemplate() {
-		Memory32Fixed (ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+		Memory32Fixed (ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
    	Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, MCH_BASE_SIZE)
    	Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, DMI_BASE_SIZE)
    	Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, EP_BASE_SIZE)
diff --git a/src/soc/intel/broadwell/include/soc/iomap.h b/src/soc/intel/broadwell/include/soc/iomap.h
index 61e53fc..4b4e3d9 100644
--- a/src/soc/intel/broadwell/include/soc/iomap.h
+++ b/src/soc/intel/broadwell/include/soc/iomap.h
@@ -15,9 +15,6 @@
 #define GDXC_BASE_ADDRESS	0xfed84000
 #define GDXC_BASE_SIZE		0x1000

-#define RCBA_BASE_ADDRESS	0xfed1c000
-#define RCBA_BASE_SIZE		0x4000
-
 #define HPET_BASE_ADDRESS	0xfed00000

#define GFXVT_BASE_ADDRESS	0xfed90000ULL
diff --git a/src/soc/intel/broadwell/include/soc/rcba.h b/src/soc/intel/broadwell/include/soc/rcba.h
index 0c63eb2..2649e9c 100644
--- a/src/soc/intel/broadwell/include/soc/rcba.h
+++ b/src/soc/intel/broadwell/include/soc/rcba.h
@@ -3,18 +3,7 @@
 #ifndef _BROADWELL_RCBA_H_
 #define _BROADWELL_RCBA_H_

-#include <soc/iomap.h>
-
-#define RCBA8(x)	*((volatile u8 *)(RCBA_BASE_ADDRESS + x))
-#define RCBA16(x)	*((volatile u16 *)(RCBA_BASE_ADDRESS + x))
-#define RCBA32(x)	*((volatile u32 *)(RCBA_BASE_ADDRESS + x))
-
-#define RCBA_AND_OR(bits, x, and, or) \
-	RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
-#define RCBA8_AND_OR(x, and, or)  RCBA_AND_OR(8, x, and, or)
-#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
-#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
-#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
+#include <southbridge/intel/common/rcba.h>

#define RPC		0x0400	/* 32bit */
 #define RPFN		0x0404	/* 32bit */
diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl
index b7d6838..0e90c95 100644
--- a/src/soc/intel/broadwell/pch/acpi/pch.asl
+++ b/src/soc/intel/broadwell/pch/acpi/pch.asl
@@ -13,7 +13,7 @@
    }

// Root Complex Register Block
-	OperationRegion (RCRB, SystemMemory, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+	OperationRegion (RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
    Field (RCRB, DWordAcc, Lock, Preserve)
    {
    	Offset (0x3404), // High Performance Timer Configuration
diff --git a/src/soc/intel/broadwell/pch/bootblock.c b/src/soc/intel/broadwell/pch/bootblock.c
index 7f6d0d5..d00a431 100644
--- a/src/soc/intel/broadwell/pch/bootblock.c
+++ b/src/soc/intel/broadwell/pch/bootblock.c
@@ -13,7 +13,7 @@

static void map_rcba(void)
 {
-	pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1);
+	pci_write_config32(PCH_DEV_LPC, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
 }

static void enable_port80_on_lpc(void)
@@ -48,7 +48,7 @@
 static void pch_enable_bars(void)
 {
    /* Set up southbridge BARs */
-	pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1);
+	pci_write_config32(PCH_DEV_LPC, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);

pci_write_config32(PCH_DEV_LPC, PMBASE, ACPI_BASE_ADDRESS | 1);

diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c
index 84b8d00..873e57e 100644
--- a/src/soc/intel/broadwell/pch/lpc.c
+++ b/src/soc/intel/broadwell/pch/lpc.c
@@ -491,10 +491,10 @@
    res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;

/* RCBA */
-	if (default_decode_base > RCBA_BASE_ADDRESS) {
+	if (default_decode_base > CONFIG_FIXED_RCBA_MMIO_BASE) {
    	res = new_resource(dev, RCBA);
-		res->base = RCBA_BASE_ADDRESS;
-		res->size = 16 * 1024;
+		res->base = CONFIG_FIXED_RCBA_MMIO_BASE;
+		res->size = CONFIG_RCBA_LENGTH;
    	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
    		     IORESOURCE_FIXED | IORESOURCE_RESERVE;
    }