Change in coreboot[master]: mb/up/squared: move USB config to device tree

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39134 )

Change subject: mb/up/squared: move USB config to device tree
......................................................................

mb/up/squared: move USB config to device tree

Change-Id: Ic4db37112e7b2329f9e4885139deca12557ffe3a
Signed-off-by: Maxim Polyakov 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39134
Reviewed-by:  Felix Singer 
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/up/squared/devicetree.cb
M src/mainboard/up/squared/ramstage.c
2 files changed, 14 insertions(+), 10 deletions(-)

Approvals:
  build bot (Jenkins): Verified
   Felix Singer: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb
index 66be75c..d7281a6 100644
--- a/src/mainboard/up/squared/devicetree.cb
+++ b/src/mainboard/up/squared/devicetree.cb
@@ -1,5 +1,19 @@
 chip soc/intel/apollolake

+	# Override USB port configuration
+	register "usb_config_override" = "1"
+	# USB 2.0
+	register "usb2_port[0]" = "PORT_EN(OC0)"
+	register "usb2_port[1]" = "PORT_EN(OC1)"
+	register "usb2_port[2]" = "PORT_EN(OC1)"
+	register "usb2_port[3]" = "PORT_EN(OC1)"
+	register "usb2_port[4]" = "PORT_EN(OC1)"
+	register "usb2_port[5]" = "PORT_EN(OC1)"
+	register "usb2_port[6]" = "PORT_EN(OC_SKIP)"
+	register "usb2_port[7]" = "PORT_EN(OC_SKIP)"
+	# USB 3.0
+	register "usb3_port[0]" = "PORT_EN(OC0)"
+
    register "enable_vtd" = "1"

device cpu_cluster 0 on
diff --git a/src/mainboard/up/squared/ramstage.c b/src/mainboard/up/squared/ramstage.c
index 637b8d8..9ae30eb 100644
--- a/src/mainboard/up/squared/ramstage.c
+++ b/src/mainboard/up/squared/ramstage.c
@@ -80,14 +80,4 @@
    silconfig->PcieRpTransmitterHalfSwing[5] = 0x0; // 0x1
    silconfig->PcieRpLtrMaxNonSnoopLatency[5] = 0x1003;	// 0x0
    silconfig->PcieRpLtrMaxSnoopLatency[5] = 0x1003;	// 0x0
-
-	silconfig->PortUs30bOverCurrentPin[0] = 0x0;	// 0x1
-
-	silconfig->PortUs20bOverCurrentPin[1] = 0x1;	// 0x0
-	silconfig->PortUs20bOverCurrentPin[2] = 0x1;	// 0x0
-	silconfig->PortUs20bOverCurrentPin[3] = 0x1;	// 0x0
-	silconfig->PortUs20bOverCurrentPin[4] = 0x1;	// 0x0
-	silconfig->PortUs20bOverCurrentPin[5] = 0x1;	// 0x0
-	silconfig->PortUs20bOverCurrentPin[6] = 0x2;	// 0x0
-	silconfig->PortUs20bOverCurrentPin[7] = 0x2;	// 0x0
 }