[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add GraniteRapids initial codes

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu.

Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email )

Change subject: soc/intel/xeon_sp: Add GraniteRapids initial codes
......................................................................

Patch Set 20:

(2 comments)

File src/soc/intel/xeon_sp/chip_gen6.c:

https://review.coreboot.org/c/coreboot/+/81316/comment/05864c27_4fc2d2b7 :
PS18, Line 145: 	soc_create_fsp24_domains(dp, upstream, sr, DOMAIN_TYPE_IOAT, pci_segment_group);
> On gen1 there are multiple PCI domains of the same type on the same stack. It works on gen1. […]

This will work, but I realized that in SPR, the domain names will be conflict with the static SSDT ASLs. I make some refactor of gen6 codes to use current way to support domain names and it looks not bad. Could you please review?

File src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h:

https://review.coreboot.org/c/coreboot/+/81316/comment/06c67e59_a39b97d3 :
PS7, Line 12:
> Yes ... they are still referenced by xeon-sp common codes. I added the tags as suggested on them.

Done