Change in coreboot[master]: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Kangheui Won, Maulik V Vaghela, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Krishna P Bhat D, Usha P.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59937 )

Change subject: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N
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Patch Set 6:

(1 comment)

File src/mainboard/intel/adlrvp/gpio_n.c:

https://review.coreboot.org/c/coreboot/+/59937/comment/9831e62e_9702a9b8 
PS5, Line 52: /*TCP1_DISP_AUX_P_BIAS_GPIO*/
            : 	PAD_CFG_GPO(GPP_E20, 1, PLTRST),
            : 	/*TCP1_DISP_AUX_N_BIAS_GPIO*/
            : 	PAD_CFG_GPO(GPP_E21, 0, PLTRST),
            : 	/*TCP0_DISP_AUX_P_BIAS_GPIO*/
            : 	PAD_CFG_GPO(GPP_E22, 0, PLTRST),
            : 	/*TCP0_DISP_AUX_N_BIAS_GPIO*/
            : 	PAD_CFG_GPO(GPP_E23, 1, PLTRST),
I am guessing here from the pad names, but should these be NF6 for AUX BIAS functionality?