Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39774 )
Change subject: soc/intel/tigerlake: Remove Jasper Lake SoC references ......................................................................
Patch Set 8:
(8 comments)
https://review.coreboot.org/c/coreboot/+/39774/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39774/7//COMMIT_MSG@10 PS7, Line 10: It also removes scs.asl since it does not apply for Tiger Lake.
This should ideally be done as a follow-up so that we start at the same baseline after the copy + cl […]
Ok, Added back
https://review.coreboot.org/c/coreboot/+/39774/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/romstage.c:
https://review.coreboot.org/c/coreboot/+/39774/6/src/mainboard/google/voltee... PS6, Line 11: #include <soc/meminit_tgl.h>
Please see my comment here: https://review.coreboot. […]
Done
https://review.coreboot.org/c/coreboot/+/39774/6/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/39774/6/src/mainboard/intel/tglrvp/... PS6, Line 20: #include <soc/meminit_tgl.h>
Agree, I tried this , but the build fails since variant.h from mainboard includes <soc/meminit. […]
Done
https://review.coreboot.org/c/coreboot/+/39774/7/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/39774/7/src/mainboard/intel/tglrvp/... PS7, Line 20: #include <soc/meminit_tgl.h>
There is no need to remove this: https://review.coreboot. […]
Done
https://review.coreboot.org/c/coreboot/+/39774/7/src/soc/intel/tigerlake/boo... File src/soc/intel/tigerlake/bootblock/pch.c:
https://review.coreboot.org/c/coreboot/+/39774/7/src/soc/intel/tigerlake/boo... PS7, Line 121: get_pmc_reg_base();
Same comment as JSL CL.
Done
https://review.coreboot.org/c/coreboot/+/39774/7/src/soc/intel/tigerlake/esp... File src/soc/intel/tigerlake/espi.c:
https://review.coreboot.org/c/coreboot/+/39774/7/src/soc/intel/tigerlake/esp... PS7, Line 83: if (lpc_did_hi_byte == 0x9D) : return PCH_LP; : else if (lpc_did_hi_byte == 0xA3) : return PCH_H; : else : return PCH_UNKNOWN_SERIES;
This doesn't look right. […]
Yes, Agree, This is not needed, removed it.
https://review.coreboot.org/c/coreboot/+/39774/7/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/meminit.h:
https://review.coreboot.org/c/coreboot/+/39774/7/src/soc/intel/tigerlake/inc... PS7, Line 8: _SOC_MEMINIT_H
This should be _SOC_MEMINIT_H_. That is the reason why build failed for you when including meminit. […]
Thanks!!. Corrected now.
https://review.coreboot.org/c/coreboot/+/39774/7/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/pch.h:
https://review.coreboot.org/c/coreboot/+/39774/7/src/soc/intel/tigerlake/inc... PS7, Line 20: #define PCH_H 1 : #define PCH_LP 2 : #define PCH_UNKNOWN_SERIES 0xFF
This has changed since before. Earlier TGL did not really consider PCH_H and PCH_LP separately. […]
Not required Furquan, removed it.
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Aamir Bohra (Code Review)