Change in coreboot[master]: sb/intel/bd82x6x: Use new PMBASE API

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27286

Change subject: sb/intel/bd82x6x: Use new PMBASE API
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sb/intel/bd82x6x: Use new PMBASE API

Change-Id: Id42bbea1f2deb0be80af2c8008045d37a926126a
Signed-off-by: Patrick Rudolph 
---
M src/southbridge/intel/bd82x6x/finalize.c
1 file changed, 2 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/27286/1

diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index 9724f08..cb3a480 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -19,15 +19,13 @@
 #include <console/post_codes.h>
 #include <cpu/x86/smm.h>
 #include <southbridge/intel/common/rcba.h>
+#include <southbridge/intel/common/pmbase.h>
 #include <spi-generic.h>
 #include "chip.h"
 #include "pch.h"

void intel_pch_finalize_smm(void)
 {
-	u16 tco1_cnt;
-	u16 pmbase;
-
    if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_RO) ||
        IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS)) {
    	/* Copy flash regions from FREG0-4 to PR0-4
@@ -72,10 +70,7 @@
    	    pci_read_config32(PCI_DEV(0, 27, 0), 0x74));

/* TCO_Lock */
-	pmbase = smm_get_pmbase();
-	tco1_cnt = inw(pmbase + TCO1_CNT);
-	tco1_cnt |= TCO_LOCK;
-	outw(tco1_cnt, pmbase + TCO1_CNT);
+	write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_LOCK);

/* Indicate finalize step with post code */
    outb(POST_OS_BOOT, 0x80);