[S] Change in coreboot[main]: soc/intel/pantherlake: Add platform debug option for FSP

[Subrata Banik (Code Review)]

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N.

Hello Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86104?usp=email

to look at the new patch set (#2).

Change subject: soc/intel/pantherlake: Add platform debug option for FSP
......................................................................

soc/intel/pantherlake: Add platform debug option for FSP

Previously, DCI was enabled unconditionally, which could interfere with
the USB data path when connected behind a powered hub and/or servo v4.1
debug connector.

This patch sets DciEn parameter based on the selected platform debug
option. If TraceHub is enabled, DciEn is set to 1. Otherwise, it is
set to 0.

BUG=b:384453901
TEST=Able to boot google/fatcat.

Change-Id: Ie77a4cc8073fdffb1b26f92597c67465e15e21d8
Signed-off-by: Subrata Banik 
---
M src/soc/intel/pantherlake/chip.h
M src/soc/intel/pantherlake/romstage/fsp_params.c
2 files changed, 28 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/86104/2