[L] Change in coreboot[main]: mb/cwwk: Add CWWK CW-ADL-4L-V1.0 board

[Brandon Weeks (Code Review)]

Attention is currently required from: Angel Pons, Federico Amedeo Izzo, Felix Singer, Joel Linn, Paul Menzel.

Brandon Weeks has posted comments on this change by Brandon Weeks. ( https://review.coreboot.org/c/coreboot/+/81595?usp=email )

Change subject: mb/cwwk: Add CWWK CW-ADL-4L-V1.0 board
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Patch Set 10:

(9 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/81595/comment/983288b3_7bc2795e?usp... :
PS9, Line 7: imb
> typo: mb

Done

https://review.coreboot.org/c/coreboot/+/81595/comment/d6cc4807_842837b0?usp... :
PS9, Line 8:
> Would be good to describe what this board is. […]

Done

https://review.coreboot.org/c/coreboot/+/81595/comment/7abcdf9b_365fbaa7?usp... :
PS9, Line 10: Memory: DDR5-4800 SODIMM (max 16 GB)
> How many DIMM slots does it have? coreboot code suggests 2, but I think it only has 1

It only has 1 DIMM slot, however I get an error during complication when DIMM_MAX is set to 1: https://gist.github.com/brandonweeks/8b8ca43791aa1fde5ab77b580723bf00

Perhaps the Alder Lake common code does not currently support a DIMM_MAX being set to 1? Or I'm doing something wrong. :)

https://review.coreboot.org/c/coreboot/+/81595/comment/4b552a70_d506438f?usp... :
PS9, Line 37: - ACPI S3 / S0ix
> For S3 you may need to enable 3VSBSW on the Super I/O

Acknowledged

File src/mainboard/cwwk/adl/Kconfig:

https://review.coreboot.org/c/coreboot/+/81595/comment/64df8653_09ec8c07?usp... :
PS9, Line 28: 	default n
> Why so? I'd at least add a comment

Removed. I will address power management in a follow up change.

https://review.coreboot.org/c/coreboot/+/81595/comment/ee00bc09_d861173e?usp... :
PS9, Line 31: 	default 5
> Why so?

Removed.

File src/mainboard/cwwk/adl/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/81595/comment/9acb38f3_1f844338?usp... :
PS9, Line 53: 		device ref crashlog off end
> Check the state of these devices in chipset. […]

Done

https://review.coreboot.org/c/coreboot/+/81595/comment/3eee0723_b35640cb?usp... :
PS9, Line 70: 		irq 0xf0 = 0x1
> nit: Add some tabs

Done

File src/mainboard/cwwk/adl/mainboard.c:

https://review.coreboot.org/c/coreboot/+/81595/comment/4effc0f3_1e58679a?usp... :
PS9, Line 8: 	params->PchEspiLgmrEnable = 0;
> Is this needed? coreboot should configure LGMR

Removed.