[XS] Change in coreboot[main]: soc/intel/alderlake: Support missing CLKREQ workaround on RaptorLake FSP

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81803?usp=email )

Change subject: soc/intel/alderlake: Support missing CLKREQ workaround on RaptorLake FSP
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soc/intel/alderlake: Support missing CLKREQ workaround on RaptorLake FSP

IoT variants of the RaptorLake FSP support the `PchPciePowerGating` and
`PchPcieClockGating` UPDs, so, remove the preprocessor check that only
enabled it for AlderLake FSPs.

Change-Id: I583a4b257b72f992fdb6390d00e187d04a749177
Signed-off-by: Benjamin Doron 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81803
Reviewed-by: Varshit Pandya 
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
Reviewed-by: Subrata Banik 
Reviewed-by: Eric Lai 
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Eric Lai: Looks good to me, approved
  Angel Pons: Looks good to me, approved
  build bot (Jenkins): Verified
  Varshit Pandya: Looks good to me, but someone else must approve
  Subrata Banik: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 33ebee3..ff5c83c 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -932,7 +932,7 @@
    }
    s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);

-#if CONFIG(FSP_TYPE_IOT) && !CONFIG(SOC_INTEL_RAPTORLAKE)
+#if CONFIG(FSP_TYPE_IOT)
    /*
     * Intel requires that all enabled PCH PCIe ports have a CLK_REQ signal connected.
     * The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1