Change in coreboot[master]: security/tpm/tss/tcg-2.0: Add `tlcl_set_bits()`

[Aseda Aboagye (Code Review)]

Attention is currently required from: Andrey Pronin, Christian Walter, Aseda Aboagye, Aaron Durbin.
Hello build bot (Jenkins), Andrey Pronin, Christian Walter, Aaron Durbin,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/55241

to look at the new patch set (#2).

Change subject: security/tpm/tss/tcg-2.0: Add `tlcl_set_bits()`
......................................................................

security/tpm/tss/tcg-2.0: Add `tlcl_set_bits()`

This commit adds support for the TPM2_NV_SetBits command to the TLCL.
This command is used to set bits in an NV index that was created as a
bit field.  Any number of bits from 0 to 64 may be set.  The contents of
bits are ORed with the current contents of the NV index.

The following is an excerpt from lalala undergoing TPM factory
initialization which exercises this function in a child commit:

```
antirollback_read_space_firmware():566: TPM: Not initialized yet.
factory_initialize_tpm():530: TPM: factory initialization
tlcl_self_test_full: response is 0
tlcl_force_clear: response is 0
tlcl_define_space: response is 14c
define_space():197: define_space: kernel space already exists
tlcl_write: response is 0
tlcl_define_space: response is 14c
define_space():197: define_space: RO MRC Hash space already exists
tlcl_write: response is 0
tlcl_define_space: response is 14c
define_space():197: define_space: FWMP space already exists
tlcl_write: response is 0
tlcl_define_space: response is 0
tlcl_write: response is 0
tlcl_define_space: response is 0
tlcl_write: response is 0
tlcl_define_space: response is 0
tlcl_set_bits: response is 0
tlcl_define_space: response is 0
tlcl_write: response is 0
factory_initialize_tpm():553: TPM: factory initialization successful
```

BUG=b:184676425
BRANCH=None
TEST=With other changes, create a NVMEM space in a TPM 2.0 TPM with the
bits attribute.  Issue the command and verify that the TPM command
succeeds.

Signed-off-by: Aseda Aboagye 
Change-Id: I6ca6376bb9f7ed8fd1167c2c80f1e8d3c3f46653
---
M src/security/tpm/tss.h
M src/security/tpm/tss/tcg-2.0/tss.c
M src/security/tpm/tss/tcg-2.0/tss_marshaling.c
M src/security/tpm/tss/tcg-2.0/tss_structures.h
4 files changed, 49 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/55241/2