Attention is currently required from: Michał Żygowski, Tim Wawrzynczak. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63467 )
Change subject: soc/intel/alderlake: add GPIO definitions for PCH-S ......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h:
https://review.coreboot.org/c/coreboot/+/63467/comment/41d479d4_18922854 PS1, Line 288: #define GPP_F20_IRQ 0x70 : #define GPP_F21_IRQ 0x71 : #define GPP_F22_IRQ 0x72 : #define GPP_F23_IRQ 0x73 : : /* Group D */ : #define GPP_D0_IRQ 0x70 : #define GPP_D1_IRQ 0x71 : #define GPP_D2_IRQ 0x72 : #define GPP_D3_IRQ 0x73
hmm, that's what doc #621483 says
So does inteltool:
``` 0x0b00: 0x0000006e84000102 GPP_F18 GPIO 0x0b10: 0x0000006f84000100 GPP_F19 GPIO 0x0b20: 0x0000007084000100 GPP_F20 GPIO 0x0b30: 0x0000007184000100 GPP_F21 GPIO 0x0b40: 0x0000007284000102 GPP_F22 GPIO 0x0b50: 0x0000007384000100 GPP_F23 GPIO ------- GPIO Community 5 -------
PCR Port ID: 0x690000
------- GPIO Group GPP_D ------- 0x0700: 0x0000007084000102 GPP_D0 GPIO 0x0710: 0x0000007184000100 GPP_D1 GPIO 0x0720: 0x0000007284000100 GPP_D2 GPIO 0x0730: 0x0000007384000100 GPP_D3 GPIO 0x0740: 0x0000007484000402 GPP_D4 SML1CLK 0x0750: 0x0000007584000a00 GPP_D5 CNV_RF_RESET# 0x0760: 0x0000007684000e00 GPP_D6 MODEM_CLKREQ ```