[M] Change in coreboot[main]: fatcat: Add 64M fmd file

[Tongtong Pan (Code Review)]

Tongtong Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86612?usp=email )

Change subject: fatcat: Add 64M fmd file
......................................................................

fatcat: Add 64M fmd file

add 64MiB size rom support on fatcat
only add size to 64M and no others flashmap change

Change-Id: I7793fbf4ece3a6c1d3ac04f89c69f956402bba10
Signed-off-by: Tongtong Pan 
---
M src/mainboard/google/fatcat/Kconfig
A src/mainboard/google/fatcat/chromeos-64M.fmd
2 files changed, 55 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/86612/1

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index e82081d..6966660 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -120,6 +120,10 @@
    default 0x01 if BOARD_GOOGLE_FRANCKA
    default 0x01 if BOARD_GOOGLE_FELINO

+config FMDFILE
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-64M.fmd" if CHROMEOS && BOARD_GOOGLE_FELINO
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
+
 config HAVE_SLP_S0_GATE
    def_bool n

diff --git a/src/mainboard/google/fatcat/chromeos-64M.fmd b/src/mainboard/google/fatcat/chromeos-64M.fmd
new file mode 100644
index 0000000..ba33cfd
--- /dev/null
+++ b/src/mainboard/google/fatcat/chromeos-64M.fmd
@@ -0,0 +1,51 @@
+
+FLASH 64M {
+	SI_ALL 8M {
+		SI_DESC 16K
+		SI_ME
+	}
+	SI_BIOS 24M {
+		RW_SECTION_A 8M {
+			VBLOCK_A 8K
+			FW_MAIN_A(CBFS)
+			RW_FWID_A 64
+		}
+		# This section starts at the 16M boundary in SPI flash.
+		# PTL does not support a region crossing this boundary,
+		# because the SPI flash is memory-mapped into two non-
+		# contiguous windows.
+		RW_SECTION_B 8M {
+			VBLOCK_B 8K
+			FW_MAIN_B(CBFS)
+			RW_FWID_B 64
+		}
+		RW_MISC 1M {
+			UNIFIED_MRC_CACHE(PRESERVE) 128K {
+				RECOVERY_MRC_CACHE 64K
+				RW_MRC_CACHE 64K
+			}
+			RW_ELOG(PRESERVE) 16K
+			RW_SHARED 16K {
+				SHARED_DATA 8K
+				VBLOCK_DEV 8K
+			}
+			RW_VPD(PRESERVE) 8K
+			RW_NVRAM(PRESERVE) 24K
+		}
+		RW_LEGACY(CBFS) 1M
+		RW_UNUSED 2M
+		# Make WP_RO region align with SPI vendor
+		# memory protected range specification.
+		WP_RO 4M {
+			RO_VPD(PRESERVE) 16K
+			RO_GSCVD 8K
+			RO_SECTION {
+				FMAP 2K
+				RO_FRID 64
+				GBB@4K 12K
+				COREBOOT(CBFS)
+			}
+		}
+	}
+}
+