Change in coreboot[master]: soc/intel/{common, skylake}: Make ASPM enabling as common PCH feature

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/29653

Change subject: soc/intel/{common, skylake}: Make ASPM enabling as common PCH feature
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soc/intel/{common, skylake}: Make ASPM enabling as common PCH feature

This patch moves required Kconfig selection for enabling ASPM feature
(like clk_pm, L1 state etc) from soc code  to intel common pch base code.

TEST=Run lspci -vvv | grep ASPM
The output shows the ASPM L1 is enable for pci devices

Change-Id: Ic77602a75f0c9ccf28ebfd57e53433dc90985a16
Signed-off-by: Subrata Banik 
---
M src/soc/intel/common/pch/Kconfig
M src/soc/intel/skylake/Kconfig
2 files changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/29653/1

diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig
index 2bf6d68..0b43b65 100644
--- a/src/soc/intel/common/pch/Kconfig
+++ b/src/soc/intel/common/pch/Kconfig
@@ -17,6 +17,10 @@

config PCH_SPECIFIC_OPTIONS
    def_bool y
+	select PCIEXP_ASPM
+	select PCIEXP_CLK_PM
+	select PCIEXP_COMMON_CLOCK
+	select PCIEXP_L1_SUB_STATE
    select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
    select SOC_INTEL_COMMON_BLOCK_CSE
    select SOC_INTEL_COMMON_BLOCK_DSP
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 2db8217..85bf904 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -40,10 +40,6 @@
    select NO_FIXED_XIP_ROM_SIZE
    select PARALLEL_MP
    select PARALLEL_MP_AP_WORK
-	select PCIEXP_ASPM
-	select PCIEXP_CLK_PM
-	select PCIEXP_COMMON_CLOCK
-	select PCIEXP_L1_SUB_STATE
    select PCIEX_LENGTH_64MB
    select REG_SCRIPT
    select RTC