[S] Change in coreboot[main]: mb/google/trulo: Support OCP fault on A0/1 ports

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82637?usp=email )

Change subject: mb/google/trulo: Support OCP fault on A0/1 ports
......................................................................

mb/google/trulo: Support OCP fault on A0/1 ports

The devicetree entry and gpio.c updated as per the schematics of Trulo
to map the OC fault signals from A0/A1 USB ports.

BUG=b:335858378
TEST= Able to build google/trulo

Change-Id: Ic17debc5eecebca8c000c43a660e1b52d2932f2a
Signed-off-by: Pranava Y N 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82637
Reviewed-by: Eric Lai 
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
Reviewed-by: Dinesh Gehlot 
---
M src/mainboard/google/brya/variants/trulo/gpio.c
M src/mainboard/google/brya/variants/trulo/overridetree.cb
2 files changed, 10 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  Eric Lai: Looks good to me, approved
  Dinesh Gehlot: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/trulo/gpio.c b/src/mainboard/google/brya/variants/trulo/gpio.c
index beee6fc..1a6d1b1 100644
--- a/src/mainboard/google/brya/variants/trulo/gpio.c
+++ b/src/mainboard/google/brya/variants/trulo/gpio.c
@@ -8,7 +8,10 @@

/* Pad configuration in ramstage */
 static const struct pad_config gpio_table[] = {
-	/* TODO */
+	/* A14 : USB_OC1# ==> USB_A0_FAULT_ODL */
+	PAD_CFG_NF_LOCK(GPP_A14, NONE, NF1, LOCK_CONFIG),
+	/* A15 : USB_OC2# ==> USB_A1_FAULT_ODL */
+	PAD_CFG_NF_LOCK(GPP_A15, NONE, NF1, LOCK_CONFIG),
 };

/* Early pad configuration in bootblock */
diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb
index ee86142..9285c33 100644
--- a/src/mainboard/google/brya/variants/trulo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb
@@ -1,4 +1,8 @@
 chip soc/intel/alderlake
-        device domain 0 on
-        end
+
+    register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type A port A0
+    register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"	# USB3/2 Type A port A1
+
+    device domain 0 on
+    end
 end