[S] Change in coreboot[master]: soc/intel/tigerlake: Select `X86_CLFLUSH_CAR` config

[Lean Sheng Tan (Code Review)]

Attention is currently required from: Tarun Tuli, Subrata Banik.

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73688 )

Change subject: soc/intel/tigerlake: Select `X86_CLFLUSH_CAR` config
......................................................................

soc/intel/tigerlake: Select `X86_CLFLUSH_CAR` config

This patch selects `X86_CLFLUSH_CAR` config for running `clflush`
to invalidate the cache region.

Signed-off-by: Lean Sheng Tan 
Change-Id: I97c8c07db9b44aa89b433e7962ec77c8501ecaa9
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/73688/1

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index d4b16c0..84425cc 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -95,6 +95,7 @@
    select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
    select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU
    select CR50_USE_LONG_INTERRUPT_PULSES if TPM_GOOGLE_CR50
+	select X86_CLFLUSH_CAR

config MAX_CPUS
    int