Change in ...coreboot[master]: mb/google/sarien/variants: Add Thermal Sensors information
Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30919
Change subject: mb/google/sarien/variants: Add Thermal Sensors information ......................................................................
mb/google/sarien/variants: Add Thermal Sensors information
Add available thermal sensors information for CPU throttling action.
BRANCH=None BUG=b:120058043 TEST=Built and tested on Arcada system
Change-Id: I748ca0ce43915c96d71e63fb03fc3d1a02adc56c Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl 2 files changed, 36 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/30919/1
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl index 2d35878..bcf6364 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl @@ -16,16 +16,24 @@ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 100
+/* Skin Sensor for CPU VR temperature monitor */ #define DPTF_TSR0_SENSOR_ID 1 -#define DPTF_TSR0_SENSOR_NAME "Thermal 1" +#define DPTF_TSR0_SENSOR_NAME "Skin" #define DPTF_TSR0_PASSIVE 55 -#define DPTF_TSR0_CRITICAL 80 +#define DPTF_TSR0_CRITICAL 70
+/* Memory Sensor for DDR temperature monitor */ #define DPTF_TSR1_SENSOR_ID 2 -#define DPTF_TSR1_SENSOR_NAME "Thermal 2" +#define DPTF_TSR1_SENSOR_NAME "DDR" #define DPTF_TSR1_PASSIVE 55 #define DPTF_TSR1_CRITICAL 80
+/* M.2 Sensor for Ambient temperature monitor */ +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "Ambient" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + #undef DPTF_ENABLE_FAN_CONTROL #undef DPTF_ENABLE_CHARGER
@@ -33,8 +41,14 @@ /* CPU Throttle Effect on CPU */ Package () { _SB.PCI0.B0D4, _SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
- /* CPU Effect on Board */ + /* CPU Throttle Effect on Skin (TSR0) */ Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on DDR (TSR1) */ + Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR2) */ + Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, })
Name (MPPC, Package () diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl index 2d35878..d63bdce 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl @@ -16,16 +16,24 @@ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 100
+/* Skin Sensor for CPU VR temperature monitor */ #define DPTF_TSR0_SENSOR_ID 1 -#define DPTF_TSR0_SENSOR_NAME "Thermal 1" +#define DPTF_TSR0_SENSOR_NAME "Skin" #define DPTF_TSR0_PASSIVE 55 -#define DPTF_TSR0_CRITICAL 80 +#define DPTF_TSR0_CRITICAL 70
+/* Memory Sensor for DDR temperature monitor */ #define DPTF_TSR1_SENSOR_ID 2 -#define DPTF_TSR1_SENSOR_NAME "Thermal 2" +#define DPTF_TSR1_SENSOR_NAME "DDR" #define DPTF_TSR1_PASSIVE 55 #define DPTF_TSR1_CRITICAL 80
+/* M.2 Sensor for Ambient temperature monitor */ +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "Ambient" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + #undef DPTF_ENABLE_FAN_CONTROL #undef DPTF_ENABLE_CHARGER
@@ -33,8 +41,14 @@ /* CPU Throttle Effect on CPU */ Package () { _SB.PCI0.B0D4, _SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
- /* CPU Effect on Board */ + /* CPU Throttle Effect on Skin (TSR0) */ Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on DDR (TSR1) */ + Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR2) */ + Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, })
Name (MPPC, Package ()
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30919 )
Change subject: mb/google/sarien/variants: Add Thermal Sensors information ......................................................................
Patch Set 1:
Please, help to review this. Thanks.
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30919 )
Change subject: mb/google/sarien/variants: Add Thermal Sensors information ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30919 )
Change subject: mb/google/sarien/variants: Add Thermal Sensors information ......................................................................
mb/google/sarien/variants: Add Thermal Sensors information
Add available thermal sensors information for CPU throttling action.
BRANCH=None BUG=b:120058043 TEST=Built and tested on Arcada system
Change-Id: I748ca0ce43915c96d71e63fb03fc3d1a02adc56c Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com Reviewed-on: https://review.coreboot.org/c/30919 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Duncan Laurie dlaurie@chromium.org --- M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl 2 files changed, 36 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl index ff59e3c..fcc8798 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl @@ -16,16 +16,24 @@ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 100
+/* Skin Sensor for CPU VR temperature monitor */ #define DPTF_TSR0_SENSOR_ID 1 -#define DPTF_TSR0_SENSOR_NAME "Thermal 1" +#define DPTF_TSR0_SENSOR_NAME "Skin" #define DPTF_TSR0_PASSIVE 55 -#define DPTF_TSR0_CRITICAL 80 +#define DPTF_TSR0_CRITICAL 70
+/* Memory Sensor for DDR temperature monitor */ #define DPTF_TSR1_SENSOR_ID 2 -#define DPTF_TSR1_SENSOR_NAME "Thermal 2" +#define DPTF_TSR1_SENSOR_NAME "DDR" #define DPTF_TSR1_PASSIVE 55 #define DPTF_TSR1_CRITICAL 80
+/* M.2 Sensor for Ambient temperature monitor */ +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "Ambient" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + #undef DPTF_ENABLE_FAN_CONTROL #undef DPTF_ENABLE_CHARGER
@@ -33,8 +41,14 @@ /* CPU Throttle Effect on CPU */ Package () { _SB.PCI0.B0D4, _SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
- /* CPU Effect on Board */ + /* CPU Throttle Effect on Skin (TSR0) */ Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on DDR (TSR1) */ + Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR2) */ + Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, })
Name (MPPC, Package () diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl index ff59e3c..459fb67 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl @@ -16,16 +16,24 @@ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 100
+/* Skin Sensor for CPU VR temperature monitor */ #define DPTF_TSR0_SENSOR_ID 1 -#define DPTF_TSR0_SENSOR_NAME "Thermal 1" +#define DPTF_TSR0_SENSOR_NAME "Skin" #define DPTF_TSR0_PASSIVE 55 -#define DPTF_TSR0_CRITICAL 80 +#define DPTF_TSR0_CRITICAL 70
+/* Memory Sensor for DDR temperature monitor */ #define DPTF_TSR1_SENSOR_ID 2 -#define DPTF_TSR1_SENSOR_NAME "Thermal 2" +#define DPTF_TSR1_SENSOR_NAME "DDR" #define DPTF_TSR1_PASSIVE 55 #define DPTF_TSR1_CRITICAL 80
+/* M.2 Sensor for Ambient temperature monitor */ +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "Ambient" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + #undef DPTF_ENABLE_FAN_CONTROL #undef DPTF_ENABLE_CHARGER
@@ -33,8 +41,14 @@ /* CPU Throttle Effect on CPU */ Package () { _SB.PCI0.B0D4, _SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
- /* CPU Effect on Board */ + /* CPU Throttle Effect on Skin (TSR0) */ Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on DDR (TSR1) */ + Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR2) */ + Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, })
Name (MPPC, Package ()
-
Duncan Laurie (Code Review) -
Patrick Georgi (Code Review)
-
Sumeet R Pawnikar (Code Review)