Change in ...coreboot[master]: soc/intel/cannonlake: SoC specific microcode update check

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31492 )

Change subject: soc/intel/cannonlake: SoC specific microcode update check
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Patch Set 2:

(5 comments)

https://review.coreboot.org/#/c/31492/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/31492/2//COMMIT_MSG@13 
PS2, Line 13: bootclock
bootblock

https://review.coreboot.org/#/c/31492/2//COMMIT_MSG@13 
PS2, Line 13: againin
again in

https://review.coreboot.org/#/c/31492/2/src/soc/intel/cannonlake/cpu.c 
File src/soc/intel/cannonlake/cpu.c:

https://review.coreboot.org/#/c/31492/2/src/soc/intel/cannonlake/cpu.c@496 
PS2, Line 496:  CFL and WHL CPU die are based on KBL CPU so we need to have this check, where CNL
This line seems to be greater than 80 columns?

https://review.coreboot.org/#/c/31492/2/src/soc/intel/cannonlake/cpu.c@504 
PS2, Line 504: *
not required

https://review.coreboot.org/#/c/31492/2/src/soc/intel/cannonlake/cpu.c@515 
PS2, Line 515: else
else not required.