Change in coreboot[master]: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch
David Jimenez has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38947 )
Change subject: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch ......................................................................
mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch
Enabling TetonGlacierMode allows for reconfiguring the PCIe lanes at runtime for hybrid drives.
BUG=b:149171631 BRANCH=none TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration
Signed-off-by: David Jimenez dvjimenez@chromium.org Change-Id: If775b40e6922ac7d111ac00c7c51eec6623ed4df --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 3 files changed, 15 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38947/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index f7cf3cd..f360c10 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -50,6 +50,8 @@ register "PchUnlockGpioPads" = "1" # SD card WP pin confguration register "ScsSdCardWpPinEnabled" = "0" + # Auto-switch between X4 NVMe and X2 NVMe for hybrid storage support + register "TetonGlacierMode" = "1"
# NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of @@ -163,7 +165,7 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN register "usb3_ports[5]" = "USB3_PORT_EMPTY"
- # Enable Root port 9(x4) for NVMe. + # Enable Root port 9(x2) for NVMe. register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 @@ -171,6 +173,10 @@ # ClkReq-to-ClkSrc mapping for CLK SRC 1 register "PcieClkSrcClkReq[1]" = "1"
+ # Enable Root port 11(x2) for NVMe hybrid storage devices. + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # PCIe port 14 for M.2 E-key WLAN register "PcieRpEnable[13]" = "1" register "PcieRpLtrEnable[13]" = "1" @@ -324,9 +330,9 @@ device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 (X4 NVME) + device pci 1d.0 on end # PCI Express Port 9 (X2 NVME) device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.2 on end # PCI Express Port 11 (x2 NVME) device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 off end # PCI Express port 13 device pci 1d.5 on diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index fd37d26..16265d2 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -242,6 +242,9 @@ * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled;
+ // Enables support for Teton Glacier hybrid storage device + uint8_t TetonGlacierMode; + /* PL1 Override value in Watts */ uint32_t tdp_pl1_override; /* PL2 Override value in Watts */ diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index dc4a2a8..e8ad62f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -374,6 +374,9 @@ #endif params->Device4Enable = config->Device4Enable;
+ /* Teton Glacier hybrid storage support */ + params->TetonGlacierMode = config->TetonGlacierMode; + /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38947 )
Change subject: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38947/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38947/1//COMMIT_MSG@9 PS1, Line 9: Enabling TetonGlacierMode allows for reconfiguring the PCIe lanes at runtime for hybrid drives. Please wrap the line after 75 or 72 characters.
https://review.coreboot.org/c/coreboot/+/38947/1/src/soc/intel/cannonlake/ch... File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/38947/1/src/soc/intel/cannonlake/ch... PS1, Line 245: // Enables support for Teton Glacier hybrid storage device For consistency, please use C89 style comments.
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38947 )
Change subject: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch ......................................................................
Patch Set 1:
Can you please separate the soc changes from the mainboard changes?
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38947 )
Change subject: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38947/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38947/1/src/mainboard/google/hatch/... PS1, Line 54: TetonGlacierMode Is there maybe a better name for this? NvmeAutoLaneCount or something?
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38947 )
Change subject: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch ......................................................................
Patch Set 1: Code-Review-1
There was some confusion here.
The patch stream to review can be found here: https://review.coreboot.org/c/coreboot/+/38846
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38947 )
Change subject: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch ......................................................................
Patch Set 1:
(2 comments)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/38947/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38947/1/src/mainboard/google/hatch/... PS1, Line 54: TetonGlacierMode
Is there maybe a better name for this? NvmeAutoLaneCount or something?
please don't.... nvme_auto_lane_count ;)
https://review.coreboot.org/c/coreboot/+/38947/1/src/mainboard/google/hatch/... PS1, Line 333: X2 x2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38947 )
Change subject: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch ......................................................................
Patch Set 1:
(6 comments)
https://review.coreboot.org/c/coreboot/+/38947/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38947/1//COMMIT_MSG@7 PS1, Line 7: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch this should be two separate changes
https://review.coreboot.org/c/coreboot/+/38947/1//COMMIT_MSG@9 PS1, Line 9: reconfiguring the PCIe lanes at runtime for hybrid drives also mention, that fsp reconfigures clkreq accordingly, too
https://review.coreboot.org/c/coreboot/+/38947/1//COMMIT_MSG@9 PS1, Line 9: TetonGlacierMode maybe add "... hybrid drives likes 'Teton Glacier' (e.g. Optane Memory H10)"
https://review.coreboot.org/c/coreboot/+/38947/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38947/1/src/mainboard/google/hatch/... PS1, Line 53: and X2 NVMe this should be 'x4 NVMe and 2x2 NVMe'
https://review.coreboot.org/c/coreboot/+/38947/1/src/mainboard/google/hatch/... PS1, Line 176: 1( mising space
https://review.coreboot.org/c/coreboot/+/38947/1/src/mainboard/google/hatch/... PS1, Line 333: X2
x2
or better x4 / 2x2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38947 )
Change subject: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch ......................................................................
Patch Set 1:
uhm. interesting. no idea why gerrit showed me this as new incoming review.... since it's already merged by CB:38846, just ignore my comments.
Maybe abandon that change to avoid further confusion?
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/38947?usp=email )
Change subject: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch ......................................................................
Abandoned
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David Jimenez (Code Review) -
Edward O'Callaghan (Code Review)
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Michael Niewöhner (Code Review)
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Paul Menzel (Code Review)
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Shelley Chen (Code Review)
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Stefan Reinauer (Code Review)
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Tim Wawrzynczak (Code Review)