Tom Hiller has uploaded this change for review. ( https://review.coreboot.org/28354
Change subject: Documentation: fix sphinx warnings ......................................................................
Documentation: fix sphinx warnings
Fix warning from list in table cells for nri_registers.md
Change-Id: I2b77ad266d1c5f693536e161f96f3db19832989c Signed-off-by: Tom Hiller thrilleratplay@gmail.com --- M Documentation/northbridge/intel/sandybridge/nri_registers.md 1 file changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/28354/1
diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md index d5857ec..e47522e 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_registers.md +++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md @@ -1522,13 +1522,20 @@ | 24:27| tWR | +-----------+------------------------------------------------------------------+ | 29 | Command 3-state options | +| | | | | - 0: Drive when channel is active, tri-state when inactive, | +| | | | | - 1: Always drive command bus | +| | | +-----------+------------------------------------------------------------------+ | 30:31| CMD stretch, | +| | | | | - 00b: 1N, | +| | | | | - 10b: 2N, | +| | | | | - 11b: 3N | +| | | +-----------+------------------------------------------------------------------+ ```
@@ -1896,14 +1903,23 @@ | | plus burst length. | +-----------+------------------------------------------------------------------+ | 8:10| PDWN_mode, selects the mode of power-down: | +| | | | | - 0x0: No power down, | +| | | | | - 0x1: APD, | +| | | | | - 0x2: PPD, | +| | | | | - 0x3: APD+PPD, | +| | | | | - 0x4: Reserved, | +| | | | | - 0x5: Reserved, | +| | | | | - 0x6: PPD-DLLoff, | +| | | | | - 0x7: APD+PPD+DLLof | +| | | +-----------+------------------------------------------------------------------+ ```
@@ -1973,19 +1989,31 @@ | Bit | Description | +===========+==================================================================+ | 0:1| CH_A, defines the largest channel. | +| | | | | - 00b: Channel 0, | +| | | | | - 01b: Channel 1, | +| | | | | - 10b: Channel 2 | +| | | +-----------+------------------------------------------------------------------+ | 2:3| CH_B, defines the mid-size channel. | +| | | | | - 00b: Channel 0, | +| | | | | - 01b: Channel 1, | +| | | | | - 10b: Channel 2 | +| | | +-----------+------------------------------------------------------------------+ | 2:3| CH_C, defines the smallest channel. | +| | | | | - 00b: Channel 0, | +| | | | | - 01b: Channel 1, | +| | | | | - 10b: Channel 2, CH_C is 10 if only 2 channels are supported | +| | | +-----------+------------------------------------------------------------------+ ```
@@ -2002,8 +2030,11 @@ | 0:7| DIMMA size in 256 MB multiples | +-----------+------------------------------------------------------------------+ | 16 | DIMM A select (DAS) Slot to DIMM mapping, | +| | | | | - 0: DIMMA, DIMMB, | +| | | | | - 1: DIMMB, DIMMA | +| | | +-----------+------------------------------------------------------------------+ | 17 | DIMM A number of ranks | +-----------+------------------------------------------------------------------+ @@ -2025,9 +2056,13 @@ | | 20-27 to use for high rank interleave | +-----------+------------------------------------------------------------------+ | 24:25| ECC, | +| | | | | - 00b: No ECC active, | +| | | | | - 01b: ECC is active on IO, | +| | | | | - 11b: ECC is active on both IO and ECC logic | +| | | +-----------+------------------------------------------------------------------+ ```
@@ -2121,7 +2156,9 @@ | Bit | Description | +===========+==================================================================+ | 0:31| Inject error when ECC_inj_Addr_Compare[31:0] = | +| | | | | ADDR[37:6] && ECC_Inj_Addr_Mask[31:0] | +| | | +-----------+------------------------------------------------------------------+ ```
@@ -2138,7 +2175,9 @@ | 0:7| Selected multiplier: 100Mhz [7,12], 133Mhz [3,19] | +-----------+------------------------------------------------------------------+ | 8 | - 1: 100Mhz reference clock | +| | | | | - 0: 133Mhz reference clock (Ivy Bridge only) | +| | | +-----------+------------------------------------------------------------------+ | 31 | PLL busy | +-----------+------------------------------------------------------------------+ @@ -2155,8 +2194,11 @@ | Bit | Description | +===========+==================================================================+ | 0:7| Active multiplier: | +| | | | | - 100Mhz [7,12], | +| | | | | - 133Mhz [3,19] | +| | | +-----------+------------------------------------------------------------------+ ```
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Tom Hiller (Code Review)