Change in coreboot[master]: mb/tglrvp: Configure intel common config

[Wonkyu Kim (Code Review)]

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40116 )

Change subject: mb/tglrvp: Configure intel common config
......................................................................

mb/tglrvp: Configure intel common config

BUG:b:151161585
BRANCH=none
TEST=build and boot tglrvp and check FSP logs to lockdown
parameters

Signed-off-by: Wonkyu Kim 
Change-Id: Id7a1e9bd94ff86faa390b5de0518e8b3cb668bff
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
2 files changed, 40 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/40116/1

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 6cef4f8..ac08225 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -122,6 +122,26 @@
    # Not disconnected/enumerable
    register "PchHdaIDispCodecDisconnect" = "0"

+	# Intel Common SoC Config
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+                .i2c[1] = {
+                        .speed = I2C_SPEED_FAST,
+                },
+                .i2c[2] = {
+                        .speed = I2C_SPEED_FAST,
+                },
+                .i2c[3] = {
+                        .speed = I2C_SPEED_FAST,
+                },
+                .i2c[5] = {
+                        .speed = I2C_SPEED_FAST,
+                },
+	}"
+
    device domain 0 on
    	#From EDS(575683)
    	device pci 00.0 on  end # Host Bridge		0x9A14:U/0x9A12:Y
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index c5cc800..d7b6a60 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -118,6 +118,26 @@
    # Not disconnected/enumerable
    register "PchHdaIDispCodecDisconnect" = "0"

+	# Intel Common SoC Config
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.i2c[0] = {
+		.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+		.speed = I2C_SPEED_FAST,
+		},
+		.i2c[2] = {
+		.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+		.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+		.speed = I2C_SPEED_FAST,
+		},
+	}"
+
    device domain 0 on
    	#From EDS(575683)
    	device pci 00.0 on  end # Host Bridge		0x9A14:U/0x9A12:Y

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40116 )

Change subject: mb/tglrvp: Configure intel common config
......................................................................

Patch Set 2: Code-Review+1

[Caveh Jalali (Code Review)]

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40116 )

Change subject: mb/tglrvp: Configure intel common config
......................................................................

Patch Set 2:

(3 comments)

https://review.coreboot.org/c/coreboot/+/40116/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40116/2//COMMIT_MSG@8 
PS2, Line 8: 
could you add a sentence or two about the lockdown and i2c mode setting?

https://review.coreboot.org/c/coreboot/+/40116/2/src/mainboard/intel/tglrvp/... 
File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/40116/2/src/mainboard/intel/tglrvp/... 
PS2, Line 131:                
tabify indentation.

https://review.coreboot.org/c/coreboot/+/40116/2/src/mainboard/intel/tglrvp/... 
File src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/40116/2/src/mainboard/intel/tglrvp/... 
PS2, Line 124: .i2c[0] = {
             : 		.speed = I2C_SPEED_FAST,
are you missing a level of indentation in these sections?

[Wonkyu Kim (Code Review)]

Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Caveh Jalali, Ravishankar Sarawadi, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40116

to look at the new patch set (#3).

Change subject: mb/tglrvp: Configure intel common config
......................................................................

mb/tglrvp: Configure intel common config

BUG:b:151161585
BRANCH=none
TEST=build and boot tglrvp and check FSP logs to lockdown
parameters

Signed-off-by: Wonkyu Kim 
Change-Id: Id7a1e9bd94ff86faa390b5de0518e8b3cb668bff
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
2 files changed, 40 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/40116/3

[Wonkyu Kim (Code Review)]

Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Caveh Jalali, Ravishankar Sarawadi, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40116

to look at the new patch set (#4).

Change subject: mb/tglrvp: Configure intel common config
......................................................................

mb/tglrvp: Configure intel common config

Configure lockdown and i2c speed setting.

BUG:b:151161585
BRANCH=none
TEST=build and boot tglrvp and check FSP logs to lockdown
parameters

Signed-off-by: Wonkyu Kim 
Change-Id: Id7a1e9bd94ff86faa390b5de0518e8b3cb668bff
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
2 files changed, 40 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/40116/4

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40116 )

Change subject: mb/tglrvp: Configure intel common config
......................................................................

Patch Set 4: Code-Review+1

(2 comments)

https://review.coreboot.org/c/coreboot/+/40116/2/src/mainboard/intel/tglrvp/... 
File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/40116/2/src/mainboard/intel/tglrvp/... 
PS2, Line 131:
> tabify indentation.

Done

https://review.coreboot.org/c/coreboot/+/40116/2/src/mainboard/intel/tglrvp/... 
File src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/40116/2/src/mainboard/intel/tglrvp/... 
PS2, Line 124: .i2c[0] = {
             : 		.speed = I2C_SPEED_FAST,
> are you missing a level of indentation in these sections?

Done

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40116 )

Change subject: mb/tglrvp: Configure intel common config
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40116/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40116/2//COMMIT_MSG@8 
PS2, Line 8:
> could you add a sentence or two about the lockdown and i2c mode setting?

Done

[Wonkyu Kim (Code Review)]

Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Caveh Jalali, Ravishankar Sarawadi, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40116

to look at the new patch set (#5).

Change subject: mb/tglrvp: Configure intel common config
......................................................................

mb/tglrvp: Configure intel common config

Configure lockdown and i2c speed setting.

BUG:b:151161585
BRANCH=none
TEST=build and boot tglrvp and check FSP logs to lockdown
parameters

Signed-off-by: Wonkyu Kim 
Change-Id: Id7a1e9bd94ff86faa390b5de0518e8b3cb668bff
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
2 files changed, 40 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/40116/5

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40116 )

Change subject: mb/tglrvp: Configure intel common config
......................................................................

Patch Set 5: Code-Review+1

[Srinidhi N Kaushik (Code Review)]

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40116 )

Change subject: mb/tglrvp: Configure intel common config
......................................................................

Patch Set 6: Code-Review+2

[Nick Vaccaro (Code Review)]

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40116 )

Change subject: mb/tglrvp: Configure intel common config
......................................................................

Patch Set 6: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40116 )

Change subject: mb/tglrvp: Configure intel common config
......................................................................

mb/tglrvp: Configure intel common config

Configure lockdown and i2c speed setting.

BUG:b:151161585
BRANCH=none
TEST=build and boot tglrvp and check FSP logs to lockdown
parameters

Signed-off-by: Wonkyu Kim 
Change-Id: Id7a1e9bd94ff86faa390b5de0518e8b3cb668bff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40116
Reviewed-by: Srinidhi N Kaushik 
Reviewed-by: Nick Vaccaro 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
2 files changed, 40 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nick Vaccaro: Looks good to me, approved
  Srinidhi N Kaushik: Looks good to me, approved
  Wonkyu Kim: Looks good to me, but someone else must approve

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 82303c6..8b4f8f8 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -128,6 +128,26 @@
    # Not disconnected/enumerable
    register "PchHdaIDispCodecDisconnect" = "0"

+	# Intel Common SoC Config
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+                },
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
    device domain 0 on
    	#From EDS(575683)
    	device pci 00.0 on  end # Host Bridge		0x9A14:U/0x9A12:Y
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 043185b..9b5774b 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -124,6 +124,26 @@
    # Not disconnected/enumerable
    register "PchHdaIDispCodecDisconnect" = "0"

+	# Intel Common SoC Config
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
    device domain 0 on
    	#From EDS(575683)
    	device pci 00.0 on  end # Host Bridge		0x9A14:U/0x9A12:Y