Change in coreboot[master]: soc/intel/common/cse: Update comment for post-CAR global world
Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37412 )
Change subject: soc/intel/common/cse: Update comment for post-CAR global world ......................................................................
soc/intel/common/cse: Update comment for post-CAR global world
Change-Id: I4ec9d7d3af1c4d7713ec5dfe516b24d110303ff1 Signed-off-by: Patrick Georgi pgeorgi@google.com --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/37412/1
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 9921825..011916d 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -146,7 +146,7 @@
static uint32_t read_bar(uint32_t offset) { - /* Reach PCI config space to get BAR in case CAR global not available */ + /* Load and cache BAR */ if (!cse.sec_bar) cse.sec_bar = get_cse_bar(); return read32((void *)(cse.sec_bar + offset)); @@ -154,7 +154,7 @@
static void write_bar(uint32_t offset, uint32_t val) { - /* Reach PCI config space to get BAR in case CAR global not available */ + /* Load and cache BAR */ if (!cse.sec_bar) cse.sec_bar = get_cse_bar(); return write32((void *)(cse.sec_bar + offset), val);
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37412 )
Change subject: soc/intel/common/cse: Update comment for post-CAR global world ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37412 )
Change subject: soc/intel/common/cse: Update comment for post-CAR global world ......................................................................
soc/intel/common/cse: Update comment for post-CAR global world
Change-Id: I4ec9d7d3af1c4d7713ec5dfe516b24d110303ff1 Signed-off-by: Patrick Georgi pgeorgi@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37412 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 9921825..011916d 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -146,7 +146,7 @@
static uint32_t read_bar(uint32_t offset) { - /* Reach PCI config space to get BAR in case CAR global not available */ + /* Load and cache BAR */ if (!cse.sec_bar) cse.sec_bar = get_cse_bar(); return read32((void *)(cse.sec_bar + offset)); @@ -154,7 +154,7 @@
static void write_bar(uint32_t offset, uint32_t val) { - /* Reach PCI config space to get BAR in case CAR global not available */ + /* Load and cache BAR */ if (!cse.sec_bar) cse.sec_bar = get_cse_bar(); return write32((void *)(cse.sec_bar + offset), val);
-
Kyösti Mälkki (Code Review) -
Patrick Georgi (Code Review)