Change in coreboot[master]: nb/intel/x4x/raminit: Initialise async variable

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19736 )

Change subject: nb/intel/x4x/raminit: Initialise async variable
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nb/intel/x4x/raminit: Initialise async variable

It could end up not initialized which causes it not to build with
clang.

Change-Id: I3be9477d836123aaa87c9bebb41c1ec34689a771
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/19736
Tested-by: build bot (Jenkins) 
Reviewed-by: Paul Menzel 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Nico Huber 
Reviewed-by: Martin Roth 
---
M src/northbridge/intel/x4x/raminit_ddr2.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Philippe Mathieu-Daudé: Looks good to me, but someone else must approve
  Paul Menzel: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  Martin Roth: Looks good to me, approved

diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c
index bb5ad61..a4a830d 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr2.c
@@ -714,7 +714,7 @@

static void dll_ddr2(struct sysinfo *s)
 {
-	u8 i, j, r, reg8, clk, async;
+	u8 i, j, r, reg8, clk, async = 0;
    u16 reg16 = 0;
    u32 reg32 = 0;
    u8 lane;