EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32952
Change subject: mb/google/sarien: Fix SSD power leakage in S5 ......................................................................
mb/google/sarien: Fix SSD power leakage in S5
Turn off SSD power in S5.
BUG=b:133389422 TEST=measure H13 is low in S5
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I40b5381cac33b0eac962a7730ee5c57e60e6d375 --- M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl 2 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/32952/1
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl index 41121d2..52e96af 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -15,6 +15,7 @@
#define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 +#define SSD_EN GPP_H13
/* Method called from LPIT prior to enter s0ix state */ Method (MS0X, 1) @@ -35,6 +36,9 @@
/* Clear touch screen pd pin to avoid leakage */ _SB.PCI0.CTXS (TS_PD) + + /* Clear SSD EN pin to avoid leakage */ + _SB.PCI0.CTXS (SSD_EN) }
/* Method called from _WAK prior to wakeup */ diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl index 41121d2..52e96af 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -15,6 +15,7 @@
#define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 +#define SSD_EN GPP_H13
/* Method called from LPIT prior to enter s0ix state */ Method (MS0X, 1) @@ -35,6 +36,9 @@
/* Clear touch screen pd pin to avoid leakage */ _SB.PCI0.CTXS (TS_PD) + + /* Clear SSD EN pin to avoid leakage */ + _SB.PCI0.CTXS (SSD_EN) }
/* Method called from _WAK prior to wakeup */
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32952 )
Change subject: mb/google/sarien: Fix SSD power leakage in S5 ......................................................................
Patch Set 5:
Please help review this.
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32952 )
Change subject: mb/google/sarien: Fix SSD power leakage in S5 ......................................................................
Patch Set 5: Code-Review+2
Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32952 )
Change subject: mb/google/sarien: Fix SSD power leakage in S5 ......................................................................
mb/google/sarien: Fix SSD power leakage in S5
Turn off SSD power in S5.
BUG=b:133389422 TEST=measure H13 is low in S5
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I40b5381cac33b0eac962a7730ee5c57e60e6d375 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32952 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Duncan Laurie dlaurie@chromium.org --- M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl 2 files changed, 16 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl index 41121d2..6eba2bc 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -15,6 +15,8 @@
#define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 +#define SSD_EN GPP_H13 +#define SSD_RST GPP_H12
/* Method called from LPIT prior to enter s0ix state */ Method (MS0X, 1) @@ -35,6 +37,12 @@
/* Clear touch screen pd pin to avoid leakage */ _SB.PCI0.CTXS (TS_PD) + + /* Clear SSD EN adn RST pin to avoid leakage */ + If (Arg0 == 5) { + _SB.PCI0.CTXS (SSD_EN) + _SB.PCI0.CTXS (SSD_RST) + } }
/* Method called from _WAK prior to wakeup */ diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl index 41121d2..6eba2bc 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -15,6 +15,8 @@
#define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 +#define SSD_EN GPP_H13 +#define SSD_RST GPP_H12
/* Method called from LPIT prior to enter s0ix state */ Method (MS0X, 1) @@ -35,6 +37,12 @@
/* Clear touch screen pd pin to avoid leakage */ _SB.PCI0.CTXS (TS_PD) + + /* Clear SSD EN adn RST pin to avoid leakage */ + If (Arg0 == 5) { + _SB.PCI0.CTXS (SSD_EN) + _SB.PCI0.CTXS (SSD_RST) + } }
/* Method called from _WAK prior to wakeup */
-
Duncan Laurie (Code Review) -
EricR Lai (Code Review)