Change in coreboot[master]: intel/block/cpu: Keep flash region cached until the payload is loaded

[Subrata Banik (Code Review)]

Attention is currently required from: Arthur Heymans, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Lean Sheng Tan, Werner Zeh, Angel Pons, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62566 )

Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded
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Patch Set 2:

(1 comment)

File src/soc/intel/common/block/cpu/mp_init.c:

https://review.coreboot.org/c/coreboot/+/62566/comment/372a91f0_2d416530 
PS2, Line 164: MP_SERVICES_PPI
> Yeah sorry for late reply. I also observed the same thing from my side. I checked the MTRR output by coreboot where the memory for SPI was not there (maybe i missed some config?) and there was always some slow moment before entering to payload. With this changes it is resolved. Already asked Intel ADL team to help verify on their side.

I could see the ROM region is already cached even without this CL (ToT image)

[DEBUG]  0x00000000ff000005: PHYBASE0: Address = 0x00000000ff000000, WP
[DEBUG]  0x00003fffff000800: PHYMASK0: Length  = 0x0000000001000000, Valid
[DEBUG]  0x00000000f9000005: PHYBASE1: Address = 0x00000000f9000000, WP
[DEBUG]  0x00003fffff000800: PHYMASK1: Length  = 0x0000000001000000, Valid
[DEBUG]  0x000000007b800006: PHYBASE2: Address = 0x000000007b800000, WB
[DEBUG]  0x00003fffff800800: PHYMASK2: Length  = 0x0000000000800000, Valid
[DEBUG]  0x0000000076000006: PHYBASE3: Address = 0x0000000076000000, WB
[DEBUG]  0x00003fffff000800: PHYMASK3: Length  = 0x0000000001000000, Valid