Change in coreboot[master]: northbridge/intel/broadwell: Add header files - coreboot-gerrit

30 May 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41937 )
Change subject: northbridge/intel/broadwell: Add header files
......................................................................
northbridge/intel/broadwell: Add header files
Relocate northbridge-related headers from soc to the northbridge scope.
Note that code in soc/intel/common expects to find `soc/systemagent.h`.
And yes, some prototypes are now in the wrong place. This will be fixed
in the next commits, once the soc/intel/broadwell subfolder is no more.
With BUILD_TIMELESS=1 but without adding the .config file into the
resulting coreboot image, google/auron (Buddy) remains identical.
Change-Id: Ia262c8734d59ed5530a9a87bb1cb0b7a86f91708
Signed-off-by: Angel Pons th3fanbus@gmail.com
---
M src/cpu/intel/broadwell/acpi.c
M src/cpu/intel/broadwell/broadwell_early_init.c
M src/cpu/intel/broadwell/cpu.c
M src/cpu/intel/broadwell/cpu_info.c
M src/cpu/intel/broadwell/romstage.c
M src/cpu/intel/broadwell/smmrelocate.c
M src/mainboard/google/auron/romstage.c
M src/mainboard/google/auron/variant.h
M src/mainboard/google/auron/variants/auron_paine/pei_data.c
M src/mainboard/google/auron/variants/auron_paine/spd/spd.c
M src/mainboard/google/auron/variants/auron_yuna/pei_data.c
M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c
M src/mainboard/google/auron/variants/buddy/pei_data.c
M src/mainboard/google/auron/variants/buddy/spd/spd.c
M src/mainboard/google/auron/variants/gandof/pei_data.c
M src/mainboard/google/auron/variants/gandof/spd/spd.c
M src/mainboard/google/auron/variants/gandof/variant.c
M src/mainboard/google/auron/variants/lulu/pei_data.c
M src/mainboard/google/auron/variants/lulu/spd/spd.c
M src/mainboard/google/auron/variants/lulu/variant.c
M src/mainboard/google/auron/variants/samus/pei_data.c
M src/mainboard/google/auron/variants/samus/spd/spd.c
M src/mainboard/google/auron/variants/samus/variant.c
M src/mainboard/google/jecht/romstage.c
M src/mainboard/google/jecht/spd/spd.c
M src/mainboard/google/jecht/variants/guado/pei_data.c
M src/mainboard/google/jecht/variants/jecht/pei_data.c
M src/mainboard/google/jecht/variants/rikku/pei_data.c
M src/mainboard/google/jecht/variants/tidus/pei_data.c
M src/mainboard/intel/wtm2/pei_data.c
M src/mainboard/intel/wtm2/romstage.c
M src/mainboard/purism/librem_bdw/romstage.c
M src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c
M src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c
M src/northbridge/intel/broadwell/bootblock.c
A src/northbridge/intel/broadwell/broadwell.h
M src/northbridge/intel/broadwell/finalize.c
M src/northbridge/intel/broadwell/igd.c
R src/northbridge/intel/broadwell/igd.h
M src/northbridge/intel/broadwell/memmap.c
M src/northbridge/intel/broadwell/minihd.c
M src/northbridge/intel/broadwell/pei_data.c
R src/northbridge/intel/broadwell/pei_data.h
R src/northbridge/intel/broadwell/pei_wrapper.h
M src/northbridge/intel/broadwell/raminit.c
M src/northbridge/intel/broadwell/refcode.c
M src/northbridge/intel/broadwell/report_platform.c
M src/northbridge/intel/broadwell/romstage.c
R src/northbridge/intel/broadwell/romstage.h
M src/northbridge/intel/broadwell/systemagent.c
M src/soc/intel/broadwell/include/soc/systemagent.h
M src/southbridge/intel/wildcatpoint/bootblock.c
M src/southbridge/intel/wildcatpoint/early_pch.c
M src/southbridge/intel/wildcatpoint/early_smbus.c
M src/southbridge/intel/wildcatpoint/power_state.c
55 files changed, 215 insertions(+), 205 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/41937/1

diff --git a/src/cpu/intel/broadwell/acpi.c b/src/cpu/intel/broadwell/acpi.c
index db5a232..c052034 100644
--- a/src/cpu/intel/broadwell/acpi.c
+++ b/src/cpu/intel/broadwell/acpi.c
@@ -21,7 +21,7 @@
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
-#include <soc/systemagent.h>
+#include <northbridge/intel/broadwell/broadwell.h>
 #include <soc/intel/broadwell/chip.h>
 #include <intelblocks/cpulib.h>
diff --git a/src/cpu/intel/broadwell/broadwell_early_init.c b/src/cpu/intel/broadwell/broadwell_early_init.c
index ad1ce6d..4fd23f6 100644
--- a/src/cpu/intel/broadwell/broadwell_early_init.c
+++ b/src/cpu/intel/broadwell/broadwell_early_init.c
@@ -4,7 +4,7 @@
 #include <console/console.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/broadwell/broadwell.h>
-#include <soc/romstage.h>
+#include <northbridge/intel/broadwell/romstage.h>
u32 cpu_family_model(void)
 {
diff --git a/src/cpu/intel/broadwell/cpu.c b/src/cpu/intel/broadwell/cpu.c
index cbb96bc..f8189dd 100644
--- a/src/cpu/intel/broadwell/cpu.c
+++ b/src/cpu/intel/broadwell/cpu.c
@@ -21,7 +21,7 @@
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 #include <soc/rcba.h>
-#include <soc/systemagent.h>
+#include <northbridge/intel/broadwell/broadwell.h>
 #include <soc/intel/broadwell/chip.h>
 #include <cpu/intel/common/common.h>
diff --git a/src/cpu/intel/broadwell/cpu_info.c b/src/cpu/intel/broadwell/cpu_info.c
index f4a8dad..975a104 100644
--- a/src/cpu/intel/broadwell/cpu_info.c
+++ b/src/cpu/intel/broadwell/cpu_info.c
@@ -3,7 +3,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/broadwell/broadwell.h>
-#include <soc/systemagent.h>
+#include <northbridge/intel/broadwell/broadwell.h>
u32 cpu_family_model(void)
 {
diff --git a/src/cpu/intel/broadwell/romstage.c b/src/cpu/intel/broadwell/romstage.c
index 54d6134..03a7e96 100644
--- a/src/cpu/intel/broadwell/romstage.c
+++ b/src/cpu/intel/broadwell/romstage.c
@@ -12,9 +12,9 @@
 #include <timestamp.h>
 #include <soc/gpio.h>
 #include <soc/me.h>
-#include <soc/pei_data.h>
+#include <northbridge/intel/broadwell/pei_data.h>
 #include <soc/pm.h>
-#include <soc/romstage.h>
+#include <northbridge/intel/broadwell/romstage.h>
 #include <soc/spi.h>
void fill_postcar_frame(struct postcar_frame *pcf)
diff --git a/src/cpu/intel/broadwell/smmrelocate.c b/src/cpu/intel/broadwell/smmrelocate.c
index 3f334d7..ea38d15 100644
--- a/src/cpu/intel/broadwell/smmrelocate.c
+++ b/src/cpu/intel/broadwell/smmrelocate.c
@@ -16,7 +16,7 @@
 #include <smp/node.h>
 #include <cpu/intel/broadwell/broadwell.h>
 #include <soc/pci_devs.h>
-#include <soc/systemagent.h>
+#include <northbridge/intel/broadwell/broadwell.h>
static void update_save_state(int cpu, uintptr_t curr_smbase,
diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c
index ed17800..1540299 100644
--- a/src/mainboard/google/auron/romstage.c
+++ b/src/mainboard/google/auron/romstage.c
@@ -2,9 +2,9 @@
#include <console/console.h>
 #include <ec/google/chromeec/ec.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
-#include <soc/romstage.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
+#include <northbridge/intel/broadwell/romstage.h>
 #include <variant/spd.h>
 #include "variant.h"
diff --git a/src/mainboard/google/auron/variant.h b/src/mainboard/google/auron/variant.h
index 095096b..9853aa2 100644
--- a/src/mainboard/google/auron/variant.h
+++ b/src/mainboard/google/auron/variant.h
@@ -4,7 +4,7 @@
 #define VARIANT_H
#include <device/device.h>
-#include <soc/romstage.h>
+#include <northbridge/intel/broadwell/romstage.h>
int variant_smbios_data(struct device *dev, int *handle,
    		unsigned long *current);
diff --git a/src/mainboard/google/auron/variants/auron_paine/pei_data.c b/src/mainboard/google/auron/variants/auron_paine/pei_data.c
index c2a22ae..88c1c28 100644
--- a/src/mainboard/google/auron/variants/auron_paine/pei_data.c
+++ b/src/mainboard/google/auron/variants/auron_paine/pei_data.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c
index da00ad9..e937651 100644
--- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c
+++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c
@@ -5,8 +5,8 @@
 #include <endian.h>
 #include <string.h>
 #include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/romstage.h>
 #include <ec/google/chromeec/ec.h>
 #include <mainboard/google/auron/ec.h>
 #include <variant/spd.h>
diff --git a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c
index c2a22ae..88c1c28 100644
--- a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c
+++ b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c
index da00ad9..e937651 100644
--- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c
+++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c
@@ -5,8 +5,8 @@
 #include <endian.h>
 #include <string.h>
 #include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/romstage.h>
 #include <ec/google/chromeec/ec.h>
 #include <mainboard/google/auron/ec.h>
 #include <variant/spd.h>
diff --git a/src/mainboard/google/auron/variants/buddy/pei_data.c b/src/mainboard/google/auron/variants/buddy/pei_data.c
index 026853f..823c968 100644
--- a/src/mainboard/google/auron/variants/buddy/pei_data.c
+++ b/src/mainboard/google/auron/variants/buddy/pei_data.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
diff --git a/src/mainboard/google/auron/variants/buddy/spd/spd.c b/src/mainboard/google/auron/variants/buddy/spd/spd.c
index 4dd1de6..fa15b34 100644
--- a/src/mainboard/google/auron/variants/buddy/spd/spd.c
+++ b/src/mainboard/google/auron/variants/buddy/spd/spd.c
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/pei_data.h>
+#include <northbridge/intel/broadwell/pei_data.h>
 #include <variant/spd.h>
/* Copy SPD data for on-board memory */
diff --git a/src/mainboard/google/auron/variants/gandof/pei_data.c b/src/mainboard/google/auron/variants/gandof/pei_data.c
index c2a22ae..88c1c28 100644
--- a/src/mainboard/google/auron/variants/gandof/pei_data.c
+++ b/src/mainboard/google/auron/variants/gandof/pei_data.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c
index da00ad9..e937651 100644
--- a/src/mainboard/google/auron/variants/gandof/spd/spd.c
+++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c
@@ -5,8 +5,8 @@
 #include <endian.h>
 #include <string.h>
 #include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/romstage.h>
 #include <ec/google/chromeec/ec.h>
 #include <mainboard/google/auron/ec.h>
 #include <variant/spd.h>
diff --git a/src/mainboard/google/auron/variants/gandof/variant.c b/src/mainboard/google/auron/variants/gandof/variant.c
index acf2a2d..bc345da 100644
--- a/src/mainboard/google/auron/variants/gandof/variant.c
+++ b/src/mainboard/google/auron/variants/gandof/variant.c
@@ -3,7 +3,7 @@
 #include <ec/google/chromeec/ec.h>
 #include <soc/pm.h>
 #include <smbios.h>
-#include <soc/romstage.h>
+#include <northbridge/intel/broadwell/romstage.h>
 #include <variant/onboard.h>
 #include <mainboard/google/auron/variant.h>
diff --git a/src/mainboard/google/auron/variants/lulu/pei_data.c b/src/mainboard/google/auron/variants/lulu/pei_data.c
index bbc7125..e88972e 100644
--- a/src/mainboard/google/auron/variants/lulu/pei_data.c
+++ b/src/mainboard/google/auron/variants/lulu/pei_data.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c
index 0daf308..7cf7e66 100644
--- a/src/mainboard/google/auron/variants/lulu/spd/spd.c
+++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c
@@ -5,8 +5,8 @@
 #include <endian.h>
 #include <string.h>
 #include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/romstage.h>
 #include <ec/google/chromeec/ec.h>
 #include <mainboard/google/auron/ec.h>
 #include <variant/spd.h>
diff --git a/src/mainboard/google/auron/variants/lulu/variant.c b/src/mainboard/google/auron/variants/lulu/variant.c
index e8b3174..98424d8 100644
--- a/src/mainboard/google/auron/variants/lulu/variant.c
+++ b/src/mainboard/google/auron/variants/lulu/variant.c
@@ -3,7 +3,7 @@
 #include <ec/google/chromeec/ec.h>
 #include <soc/pm.h>
 #include <smbios.h>
-#include <soc/romstage.h>
+#include <northbridge/intel/broadwell/romstage.h>
 #include <variant/onboard.h>
 #include <mainboard/google/auron/variant.h>
diff --git a/src/mainboard/google/auron/variants/samus/pei_data.c b/src/mainboard/google/auron/variants/samus/pei_data.c
index 9bcf92b..eef54d4 100644
--- a/src/mainboard/google/auron/variants/samus/pei_data.c
+++ b/src/mainboard/google/auron/variants/samus/pei_data.c
@@ -3,8 +3,8 @@
 #include <stdint.h>
 #include <string.h>
 #include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c
index 4684d86..213d4a5 100644
--- a/src/mainboard/google/auron/variants/samus/spd/spd.c
+++ b/src/mainboard/google/auron/variants/samus/spd/spd.c
@@ -5,8 +5,8 @@
 #include <endian.h>
 #include <string.h>
 #include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/romstage.h>
 #include <ec/google/chromeec/ec.h>
 #include <mainboard/google/auron/ec.h>
 #include <variant/spd.h>
diff --git a/src/mainboard/google/auron/variants/samus/variant.c b/src/mainboard/google/auron/variants/samus/variant.c
index 12f4e86..baa0d52 100644
--- a/src/mainboard/google/auron/variants/samus/variant.c
+++ b/src/mainboard/google/auron/variants/samus/variant.c
@@ -4,7 +4,7 @@
 #include <ec/google/chromeec/ec.h>
 #include <soc/gpio.h>
 #include <soc/pm.h>
-#include <soc/romstage.h>
+#include <northbridge/intel/broadwell/romstage.h>
 #include <smbios.h>
 #include <variant/board_version.h>
 #include <variant/onboard.h>
diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c
index 1f03aed..0b30542 100644
--- a/src/mainboard/google/jecht/romstage.c
+++ b/src/mainboard/google/jecht/romstage.c
@@ -3,9 +3,9 @@
 #include <bootmode.h>
 #include <console/console.h>
 #include <ec/google/chromeec/ec.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
-#include <soc/romstage.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
+#include <northbridge/intel/broadwell/romstage.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8772f/it8772f.h>
 #include <mainboard/google/jecht/spd/spd.h>
diff --git a/src/mainboard/google/jecht/spd/spd.c b/src/mainboard/google/jecht/spd/spd.c
index 911cf60..342f311 100644
--- a/src/mainboard/google/jecht/spd/spd.c
+++ b/src/mainboard/google/jecht/spd/spd.c
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/pei_data.h>
+#include <northbridge/intel/broadwell/pei_data.h>
 #include <mainboard/google/jecht/spd/spd.h>
/* Copy SPD data for on-board memory */
diff --git a/src/mainboard/google/jecht/variants/guado/pei_data.c b/src/mainboard/google/jecht/variants/guado/pei_data.c
index ba950d6..1efb768 100644
--- a/src/mainboard/google/jecht/variants/guado/pei_data.c
+++ b/src/mainboard/google/jecht/variants/guado/pei_data.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
diff --git a/src/mainboard/google/jecht/variants/jecht/pei_data.c b/src/mainboard/google/jecht/variants/jecht/pei_data.c
index ba950d6..1efb768 100644
--- a/src/mainboard/google/jecht/variants/jecht/pei_data.c
+++ b/src/mainboard/google/jecht/variants/jecht/pei_data.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
diff --git a/src/mainboard/google/jecht/variants/rikku/pei_data.c b/src/mainboard/google/jecht/variants/rikku/pei_data.c
index ba950d6..1efb768 100644
--- a/src/mainboard/google/jecht/variants/rikku/pei_data.c
+++ b/src/mainboard/google/jecht/variants/rikku/pei_data.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
diff --git a/src/mainboard/google/jecht/variants/tidus/pei_data.c b/src/mainboard/google/jecht/variants/tidus/pei_data.c
index dc13022..6af5d83 100644
--- a/src/mainboard/google/jecht/variants/tidus/pei_data.c
+++ b/src/mainboard/google/jecht/variants/tidus/pei_data.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
diff --git a/src/mainboard/intel/wtm2/pei_data.c b/src/mainboard/intel/wtm2/pei_data.c
index 92101bd..bcf091a 100644
--- a/src/mainboard/intel/wtm2/pei_data.c
+++ b/src/mainboard/intel/wtm2/pei_data.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c
index 9e22250..9fc63cf 100644
--- a/src/mainboard/intel/wtm2/romstage.c
+++ b/src/mainboard/intel/wtm2/romstage.c
@@ -2,9 +2,9 @@
#include <console/console.h>
 #include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
-#include <soc/romstage.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
+#include <northbridge/intel/broadwell/romstage.h>
void mainboard_pre_raminit(struct romstage_params *rp)
 {
diff --git a/src/mainboard/purism/librem_bdw/romstage.c b/src/mainboard/purism/librem_bdw/romstage.c
index 8fc2f9e..41447c9 100644
--- a/src/mainboard/purism/librem_bdw/romstage.c
+++ b/src/mainboard/purism/librem_bdw/romstage.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
-#include <soc/romstage.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
+#include <northbridge/intel/broadwell/romstage.h>
void mainboard_pre_raminit(struct romstage_params *rp)
 {
diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c b/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c
index 1e5d9d9..6fe5584 100644
--- a/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c
+++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c b/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c
index c3580b3..2a61fe6 100644
--- a/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c
+++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
diff --git a/src/northbridge/intel/broadwell/bootblock.c b/src/northbridge/intel/broadwell/bootblock.c
index ef55699..be389b7 100644
--- a/src/northbridge/intel/broadwell/bootblock.c
+++ b/src/northbridge/intel/broadwell/bootblock.c
@@ -3,7 +3,7 @@
 #include <arch/bootblock.h>
 #include <device/pci_ops.h>
 #include <soc/pci_devs.h>
-#include <soc/systemagent.h>
+#include <northbridge/intel/broadwell/broadwell.h>
void bootblock_early_northbridge_init(void)
 {
diff --git a/src/northbridge/intel/broadwell/broadwell.h b/src/northbridge/intel/broadwell/broadwell.h
new file mode 100644
index 0000000..8d71103
--- /dev/null
+++ b/src/northbridge/intel/broadwell/broadwell.h
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __NORTHBRIDGE_INTEL_BROADWELL_BROADWELL_H__
+#define __NORTHBRIDGE_INTEL_BROADWELL_BROADWELL_H__
+
+#include <soc/iomap.h>
+
+#define SA_IGD_OPROM_VENDEV	0x80860406
+
+#define IGD_HASWELL_ULT_GT1	0x0a06
+#define IGD_HASWELL_ULT_GT2	0x0a16
+#define IGD_HASWELL_ULT_GT3	0x0a26
+#define IGD_HASWELL_ULX_GT1	0x0a0e
+#define IGD_HASWELL_ULX_GT2	0x0a1e
+#define IGD_BROADWELL_U_GT1	0x1606
+#define IGD_BROADWELL_U_GT2	0x1616
+#define IGD_BROADWELL_U_GT3_15W	0x1626
+#define IGD_BROADWELL_U_GT3_28W	0x162b
+#define IGD_BROADWELL_Y_GT2	0x161e
+#define IGD_BROADWELL_H_GT2	0x1612
+#define IGD_BROADWELL_H_GT3	0x1622
+
+#define MCH_BROADWELL_ID_U_Y	0x1604
+#define MCH_BROADWELL_REV_D0	0x06
+#define MCH_BROADWELL_REV_E0	0x08
+#define MCH_BROADWELL_REV_F0	0x09
+
+/* Device 0:0.0 PCI configuration space */
+
+#define EPBAR		0x40
+#define MCHBAR		0x48
+#define PCIEXBAR	0x60
+#define DMIBAR		0x68
+#define GGC		0x50	/* GMCH Graphics Control */
+#define DEVEN		0x54	/* Device Enable */
+#define  DEVEN_D7EN	(1 << 14)
+#define  DEVEN_D4EN	(1 << 7)
+#define  DEVEN_D3EN	(1 << 5)
+#define  DEVEN_D2EN	(1 << 4)
+#define  DEVEN_D1F0EN	(1 << 3)
+#define  DEVEN_D1F1EN	(1 << 2)
+#define  DEVEN_D1F2EN	(1 << 1)
+#define  DEVEN_D0EN	(1 << 0)
+#define DPR		0x5c
+#define  DPR_EPM	(1 << 2)
+#define  DPR_PRS	(1 << 1)
+#define  DPR_SIZE_MASK	0xff0
+
+#define PAM0		0x80
+#define PAM1		0x81
+#define PAM2		0x82
+#define PAM3		0x83
+#define PAM4		0x84
+#define PAM5		0x85
+#define PAM6		0x86
+
+#define SMRAM		0x88	/* System Management RAM Control */
+#define  D_OPEN		(1 << 6)
+#define  D_CLS		(1 << 5)
+#define  D_LCK		(1 << 4)
+#define  G_SMRAME	(1 << 3)
+#define  C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
+#define CAPID0_A	0xe4
+#define  VTD_DISABLE	(1 << 23)
+#define ARCHDIS		0xff0	/* DMA Remap Engine Policy Control */
+#define  DMAR_LCKDN	(1 << 31)
+#define  PRSCAPDIS	(1 << 2)
+
+#define MESEG_BASE	0x70	/* Management Engine Base. */
+#define MESEG_LIMIT	0x78	/* Management Engine Limit. */
+#define REMAPBASE	0x90	/* Remap base. */
+#define REMAPLIMIT	0x98	/* Remap limit. */
+#define TOM		0xa0	/* Top of DRAM in memory controller space. */
+#define TOUUD		0xa8	/* Top of Upper Usable DRAM */
+#define BDSM		0xb0	/* Base Data Stolen Memory */
+#define BGSM		0xb4	/* Base GTT Stolen Memory */
+#define TSEG		0xb8	/* TSEG base */
+#define TOLUD		0xbc	/* Top of Low Used Memory */
+#define SKPAD		0xdc	/* Scratchpad Data */
+
+/* MCHBAR */
+
+#define MCHBAR8(x)	*((volatile u8 *)(MCH_BASE_ADDRESS + x))
+#define MCHBAR16(x)	*((volatile u16 *)(MCH_BASE_ADDRESS + x))
+#define MCHBAR32(x)	*((volatile u32 *)(MCH_BASE_ADDRESS + x))
+
+#define MCHBAR_PEI_VERSION	0x5034
+#define BIOS_RESET_CPL		0x5da8
+#define GFXVTBAR		0x5400
+#define EDRAMBAR		0x5408
+#define VTVC0BAR		0x5410
+#define MCH_PAIR		0x5418
+#define GDXCBAR			0x5420
+
+#define MCH_PKG_POWER_LIMIT_LO	0x59a0
+#define MCH_PKG_POWER_LIMIT_HI	0x59a4
+#define MCH_DDR_POWER_LIMIT_LO	0x58e0
+#define MCH_DDR_POWER_LIMIT_HI	0x58e4
+
+/* PCODE MMIO communications live in the MCHBAR. */
+#define BIOS_MAILBOX_INTERFACE			0x5da4
+#define  MAILBOX_RUN_BUSY			(1 << 31)
+#define  MAILBOX_BIOS_CMD_READ_PCS		1
+#define  MAILBOX_BIOS_CMD_WRITE_PCS		2
+#define  MAILBOX_BIOS_CMD_READ_CALIBRATION	0x509
+#define  MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL	0x909
+#define  MAILBOX_BIOS_CMD_READ_PCH_POWER	0xa
+#define  MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT	0xb
+#define  MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE	0x26
+#define  MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE	0x27
+/* Errors are returned back in bits 7:0. */
+#define  MAILBOX_BIOS_ERROR_NONE		0
+#define  MAILBOX_BIOS_ERROR_INVALID_COMMAND	1
+#define  MAILBOX_BIOS_ERROR_TIMEOUT		2
+#define  MAILBOX_BIOS_ERROR_ILLEGAL_DATA	3
+#define  MAILBOX_BIOS_ERROR_RESERVED		4
+#define  MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID	5
+#define  MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED	6
+#define  MAILBOX_BIOS_ERROR_VR_ERROR		7
+/* Data is passed through bits 31:0 of the data register. */
+#define BIOS_MAILBOX_DATA			0x5da0
+
+/* System Agent identification */
+u8 systemagent_revision(void);
+
+uintptr_t sa_get_tolud_base(void);
+uintptr_t sa_get_gsm_base(void);
+
+#endif
diff --git a/src/northbridge/intel/broadwell/finalize.c b/src/northbridge/intel/broadwell/finalize.c
index 35ce010..d258694 100644
--- a/src/northbridge/intel/broadwell/finalize.c
+++ b/src/northbridge/intel/broadwell/finalize.c
@@ -11,7 +11,7 @@
 #include <soc/me.h>
 #include <soc/rcba.h>
 #include <soc/spi.h>
-#include <soc/systemagent.h>
+#include <northbridge/intel/broadwell/broadwell.h>
 #include <southbridge/intel/common/spi.h>
const struct reg_script system_agent_finalize_script[] = {
diff --git a/src/northbridge/intel/broadwell/igd.c b/src/northbridge/intel/broadwell/igd.c
index 5f6673f..3e47b53 100644
--- a/src/northbridge/intel/broadwell/igd.c
+++ b/src/northbridge/intel/broadwell/igd.c
@@ -18,10 +18,10 @@
 #include <cpu/intel/broadwell/broadwell.h>
 #include <soc/pm.h>
 #include <soc/ramstage.h>
-#include <soc/systemagent.h>
+#include <northbridge/intel/broadwell/broadwell.h>
 #include <soc/intel/broadwell/chip.h>
 #include <security/vboot/vbnv.h>
-#include <soc/igd.h>
+#include <northbridge/intel/broadwell/igd.h>
 #include <types.h>
#define GT_RETRY		1000
diff --git a/src/soc/intel/broadwell/include/soc/igd.h b/src/northbridge/intel/broadwell/igd.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/igd.h
rename to src/northbridge/intel/broadwell/igd.h
diff --git a/src/northbridge/intel/broadwell/memmap.c b/src/northbridge/intel/broadwell/memmap.c
index bada5fd..c062d7d 100644
--- a/src/northbridge/intel/broadwell/memmap.c
+++ b/src/northbridge/intel/broadwell/memmap.c
@@ -7,7 +7,7 @@
 #include <device/pci.h>
 #include <device/pci_ops.h>
 #include <soc/pci_devs.h>
-#include <soc/systemagent.h>
+#include <northbridge/intel/broadwell/broadwell.h>
 #include <stdint.h>
static uintptr_t dpr_region_start(void)
diff --git a/src/northbridge/intel/broadwell/minihd.c b/src/northbridge/intel/broadwell/minihd.c
index b91d73d..db15dbb 100644
--- a/src/northbridge/intel/broadwell/minihd.c
+++ b/src/northbridge/intel/broadwell/minihd.c
@@ -8,7 +8,7 @@
 #include <device/mmio.h>
 #include <soc/intel/common/hda_verb.h>
 #include <soc/ramstage.h>
-#include <soc/igd.h>
+#include <northbridge/intel/broadwell/igd.h>
static const u32 minihd_verb_table[] = {
    /* coreboot specific header */
diff --git a/src/northbridge/intel/broadwell/pei_data.c b/src/northbridge/intel/broadwell/pei_data.c
index efc91fd..41fc475 100644
--- a/src/northbridge/intel/broadwell/pei_data.c
+++ b/src/northbridge/intel/broadwell/pei_data.c
@@ -2,8 +2,8 @@
#include <console/streams.h>
 #include <soc/iomap.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
static void ABI_X86 send_to_console(unsigned char b)
 {
diff --git a/src/soc/intel/broadwell/include/soc/pei_data.h b/src/northbridge/intel/broadwell/pei_data.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/pei_data.h
rename to src/northbridge/intel/broadwell/pei_data.h
diff --git a/src/soc/intel/broadwell/include/soc/pei_wrapper.h b/src/northbridge/intel/broadwell/pei_wrapper.h
similarity index 94%
rename from src/soc/intel/broadwell/include/soc/pei_wrapper.h
rename to src/northbridge/intel/broadwell/pei_wrapper.h
index 81e1bd5..44c23d0 100644
--- a/src/soc/intel/broadwell/include/soc/pei_wrapper.h
+++ b/src/northbridge/intel/broadwell/pei_wrapper.h
@@ -3,7 +3,7 @@
 #ifndef _BROADWELL_PEI_WRAPPER_H_
 #define _BROADWELL_PEI_WRAPPER_H_
-#include <soc/pei_data.h>
+#include <northbridge/intel/broadwell/pei_data.h>
typedef int ABI_X86 (*pei_wrapper_entry_t)(struct pei_data *pei_data);
diff --git a/src/northbridge/intel/broadwell/raminit.c b/src/northbridge/intel/broadwell/raminit.c
index 8c194fc..dca56b6 100644
--- a/src/northbridge/intel/broadwell/raminit.c
+++ b/src/northbridge/intel/broadwell/raminit.c
@@ -15,11 +15,11 @@
 #endif
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/iomap.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
 #include <soc/pm.h>
-#include <soc/romstage.h>
-#include <soc/systemagent.h>
+#include <northbridge/intel/broadwell/romstage.h>
+#include <northbridge/intel/broadwell/broadwell.h>
/*
  * Find PEI executable in coreboot filesystem and execute it.
diff --git a/src/northbridge/intel/broadwell/refcode.c b/src/northbridge/intel/broadwell/refcode.c
index 5e5bc49..5ba43cd 100644
--- a/src/northbridge/intel/broadwell/refcode.c
+++ b/src/northbridge/intel/broadwell/refcode.c
@@ -9,8 +9,8 @@
 #include <program_loading.h>
 #include <rmodule.h>
 #include <stage_cache.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
+#include <northbridge/intel/broadwell/pei_data.h>
+#include <northbridge/intel/broadwell/pei_wrapper.h>
 #include <soc/pm.h>
 #include <soc/ramstage.h>
diff --git a/src/northbridge/intel/broadwell/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c
index 88228f9..1012ce2 100644
--- a/src/northbridge/intel/broadwell/report_platform.c
+++ b/src/northbridge/intel/broadwell/report_platform.c
@@ -9,8 +9,8 @@
 #include <cpu/intel/broadwell/broadwell.h>
 #include <soc/pch.h>
 #include <soc/pci_devs.h>
-#include <soc/romstage.h>
-#include <soc/systemagent.h>
+#include <northbridge/intel/broadwell/romstage.h>
+#include <northbridge/intel/broadwell/broadwell.h>
static struct {
    u32 cpuid;
diff --git a/src/northbridge/intel/broadwell/romstage.c b/src/northbridge/intel/broadwell/romstage.c
index 6f6db62..efc26d9 100644
--- a/src/northbridge/intel/broadwell/romstage.c
+++ b/src/northbridge/intel/broadwell/romstage.c
@@ -6,8 +6,8 @@
 #include <reg_script.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
-#include <soc/romstage.h>
-#include <soc/systemagent.h>
+#include <northbridge/intel/broadwell/romstage.h>
+#include <northbridge/intel/broadwell/broadwell.h>
static const struct reg_script systemagent_early_init_script[] = {
    REG_PCI_WRITE32(MCHBAR, MCH_BASE_ADDRESS | 1),
diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/northbridge/intel/broadwell/romstage.h
similarity index 93%
rename from src/soc/intel/broadwell/include/soc/romstage.h
rename to src/northbridge/intel/broadwell/romstage.h
index 2c7b0a4..275938a 100644
--- a/src/soc/intel/broadwell/include/soc/romstage.h
+++ b/src/northbridge/intel/broadwell/romstage.h
@@ -4,7 +4,7 @@
 #define _BROADWELL_ROMSTAGE_H_
#include <stdint.h>
-#include <soc/pei_data.h>
+#include <northbridge/intel/broadwell/pei_data.h>
struct chipset_power_state;
 struct romstage_params {
diff --git a/src/northbridge/intel/broadwell/systemagent.c b/src/northbridge/intel/broadwell/systemagent.c
index b75c4fe..15110da 100644
--- a/src/northbridge/intel/broadwell/systemagent.c
+++ b/src/northbridge/intel/broadwell/systemagent.c
@@ -14,7 +14,7 @@
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
-#include <soc/systemagent.h>
+#include <northbridge/intel/broadwell/broadwell.h>
u8 systemagent_revision(void)
 {
diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h
index c2c5cc8..5c93352 100644
--- a/src/soc/intel/broadwell/include/soc/systemagent.h
+++ b/src/soc/intel/broadwell/include/soc/systemagent.h
@@ -5,125 +5,6 @@
#include <soc/iomap.h>
-#define SA_IGD_OPROM_VENDEV	0x80860406
-
-#define IGD_HASWELL_ULT_GT1	0x0a06
-#define IGD_HASWELL_ULT_GT2	0x0a16
-#define IGD_HASWELL_ULT_GT3	0x0a26
-#define IGD_HASWELL_ULX_GT1	0x0a0e
-#define IGD_HASWELL_ULX_GT2	0x0a1e
-#define IGD_BROADWELL_U_GT1	0x1606
-#define IGD_BROADWELL_U_GT2	0x1616
-#define IGD_BROADWELL_U_GT3_15W	0x1626
-#define IGD_BROADWELL_U_GT3_28W	0x162b
-#define IGD_BROADWELL_Y_GT2	0x161e
-#define IGD_BROADWELL_H_GT2	0x1612
-#define IGD_BROADWELL_H_GT3	0x1622
-
-#define MCH_BROADWELL_ID_U_Y	0x1604
-#define MCH_BROADWELL_REV_D0	0x06
-#define MCH_BROADWELL_REV_E0	0x08
-#define MCH_BROADWELL_REV_F0	0x09
-
-/* Device 0:0.0 PCI configuration space */
-
-#define EPBAR		0x40
-#define MCHBAR		0x48
-#define PCIEXBAR	0x60
-#define DMIBAR		0x68
-#define GGC		0x50	/* GMCH Graphics Control */
-#define DEVEN		0x54	/* Device Enable */
-#define  DEVEN_D7EN	(1 << 14)
-#define  DEVEN_D4EN	(1 << 7)
-#define  DEVEN_D3EN	(1 << 5)
-#define  DEVEN_D2EN	(1 << 4)
-#define  DEVEN_D1F0EN	(1 << 3)
-#define  DEVEN_D1F1EN	(1 << 2)
-#define  DEVEN_D1F2EN	(1 << 1)
-#define  DEVEN_D0EN	(1 << 0)
-#define DPR		0x5c
-#define  DPR_EPM	(1 << 2)
-#define  DPR_PRS	(1 << 1)
-#define  DPR_SIZE_MASK	0xff0
-
-#define PAM0		0x80
-#define PAM1		0x81
-#define PAM2		0x82
-#define PAM3		0x83
-#define PAM4		0x84
-#define PAM5		0x85
-#define PAM6		0x86
-
-#define SMRAM		0x88	/* System Management RAM Control */
-#define  D_OPEN		(1 << 6)
-#define  D_CLS		(1 << 5)
-#define  D_LCK		(1 << 4)
-#define  G_SMRAME	(1 << 3)
-#define  C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
-#define CAPID0_A	0xe4
-#define  VTD_DISABLE	(1 << 23)
-#define ARCHDIS		0xff0	/* DMA Remap Engine Policy Control */
-#define  DMAR_LCKDN	(1 << 31)
-#define  PRSCAPDIS	(1 << 2)
-
-#define MESEG_BASE	0x70	/* Management Engine Base. */
-#define MESEG_LIMIT	0x78	/* Management Engine Limit. */
-#define REMAPBASE	0x90	/* Remap base. */
-#define REMAPLIMIT	0x98	/* Remap limit. */
-#define TOM		0xa0	/* Top of DRAM in memory controller space. */
-#define TOUUD		0xa8	/* Top of Upper Usable DRAM */
-#define BDSM		0xb0	/* Base Data Stolen Memory */
-#define BGSM		0xb4	/* Base GTT Stolen Memory */
-#define TSEG		0xb8	/* TSEG base */
-#define TOLUD		0xbc	/* Top of Low Used Memory */
-#define SKPAD		0xdc	/* Scratchpad Data */
-
-/* MCHBAR */
-
-#define MCHBAR8(x)	*((volatile u8 *)(MCH_BASE_ADDRESS + x))
-#define MCHBAR16(x)	*((volatile u16 *)(MCH_BASE_ADDRESS + x))
 #define MCHBAR32(x)	*((volatile u32 *)(MCH_BASE_ADDRESS + x))
-#define MCHBAR_PEI_VERSION	0x5034
-#define BIOS_RESET_CPL		0x5da8
-#define GFXVTBAR		0x5400
-#define EDRAMBAR		0x5408
-#define VTVC0BAR		0x5410
-#define MCH_PAIR		0x5418
-#define GDXCBAR			0x5420
-
-#define MCH_PKG_POWER_LIMIT_LO	0x59a0
-#define MCH_PKG_POWER_LIMIT_HI	0x59a4
-#define MCH_DDR_POWER_LIMIT_LO	0x58e0
-#define MCH_DDR_POWER_LIMIT_HI	0x58e4
-
-/* PCODE MMIO communications live in the MCHBAR. */
-#define BIOS_MAILBOX_INTERFACE			0x5da4
-#define  MAILBOX_RUN_BUSY			(1 << 31)
-#define  MAILBOX_BIOS_CMD_READ_PCS		1
-#define  MAILBOX_BIOS_CMD_WRITE_PCS		2
-#define  MAILBOX_BIOS_CMD_READ_CALIBRATION	0x509
-#define  MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL	0x909
-#define  MAILBOX_BIOS_CMD_READ_PCH_POWER	0xa
-#define  MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT	0xb
-#define  MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE	0x26
-#define  MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE	0x27
-/* Errors are returned back in bits 7:0. */
-#define  MAILBOX_BIOS_ERROR_NONE		0
-#define  MAILBOX_BIOS_ERROR_INVALID_COMMAND	1
-#define  MAILBOX_BIOS_ERROR_TIMEOUT		2
-#define  MAILBOX_BIOS_ERROR_ILLEGAL_DATA	3
-#define  MAILBOX_BIOS_ERROR_RESERVED		4
-#define  MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID	5
-#define  MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED	6
-#define  MAILBOX_BIOS_ERROR_VR_ERROR		7
-/* Data is passed through bits 31:0 of the data register. */
-#define BIOS_MAILBOX_DATA			0x5da0
-
-/* System Agent identification */
-u8 systemagent_revision(void);
-
-uintptr_t sa_get_tolud_base(void);
-uintptr_t sa_get_gsm_base(void);
-
 #endif
diff --git a/src/southbridge/intel/wildcatpoint/bootblock.c b/src/southbridge/intel/wildcatpoint/bootblock.c
index c7b3e67..61af770 100644
--- a/src/southbridge/intel/wildcatpoint/bootblock.c
+++ b/src/southbridge/intel/wildcatpoint/bootblock.c
@@ -9,7 +9,7 @@
 #include <soc/spi.h>
 #include <reg_script.h>
 #include <soc/pm.h>
-#include <soc/romstage.h>
+#include <northbridge/intel/broadwell/romstage.h>
/*
  * Enable Prefetching and Caching.
diff --git a/src/southbridge/intel/wildcatpoint/early_pch.c b/src/southbridge/intel/wildcatpoint/early_pch.c
index 9afb4e4..9b73760 100644
--- a/src/southbridge/intel/wildcatpoint/early_pch.c
+++ b/src/southbridge/intel/wildcatpoint/early_pch.c
@@ -11,7 +11,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/rcba.h>
-#include <soc/romstage.h>
+#include <northbridge/intel/broadwell/romstage.h>
 #include <soc/smbus.h>
 #include <soc/intel/broadwell/chip.h>
diff --git a/src/southbridge/intel/wildcatpoint/early_smbus.c b/src/southbridge/intel/wildcatpoint/early_smbus.c
index a000255..5da5f4e 100644
--- a/src/southbridge/intel/wildcatpoint/early_smbus.c
+++ b/src/southbridge/intel/wildcatpoint/early_smbus.c
@@ -6,7 +6,7 @@
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
 #include <soc/smbus.h>
-#include <soc/romstage.h>
+#include <northbridge/intel/broadwell/romstage.h>
static const struct reg_script smbus_init_script[] = {
    /* Set SMBUS I/O base address */
diff --git a/src/southbridge/intel/wildcatpoint/power_state.c b/src/southbridge/intel/wildcatpoint/power_state.c
index 8128458..b9263b4 100644
--- a/src/southbridge/intel/wildcatpoint/power_state.c
+++ b/src/southbridge/intel/wildcatpoint/power_state.c
@@ -13,7 +13,7 @@
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
-#include <soc/romstage.h>
+#include <northbridge/intel/broadwell/romstage.h>
static struct chipset_power_state power_state;
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ia262c8734d59ed5530a9a87bb1cb0b7a86f91708
Gerrit-Change-Number: 41937
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons th3fanbus@gmail.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-MessageType: newchange



    