Change in coreboot[master]: soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59826 )

Change subject: soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake
......................................................................

soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake

Check the Alderlake CPU ID to determine if cse sub-paritition update is
required or not.

BUG=b:202143532

Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831
Signed-off-by: Krishna Prasad Bhat 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59826
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/alderlake/romstage/romstage.c
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index d33d21f..b9d08c8 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -15,6 +15,7 @@
 #include <soc/pm.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
+#include <cpu/intel/cpu_ids.h>
 #include <string.h>

#define FSP_SMBIOS_MEMORY_INFO_GUID	\
@@ -23,6 +24,11 @@
    0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23	\
 }

+bool skip_cse_sub_part_update(void)
+{
+	return cpu_get_cpuid() != CPUID_ALDERLAKE_A2;
+}
+
 /* Save the DIMM information for SMBIOS table 17 */
 static void save_dimm_info(void)
 {

4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.