Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45129 )
Change subject: [NOT FOR MERGE] mb/clevo/n130wu: Make master working ......................................................................
[NOT FOR MERGE] mb/clevo/n130wu: Make master working
Change-Id: I30b4af7430c4b80d03e9601ef9d81d1624f0be87 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Makefile.inc M src/mainboard/clevo/kbl-u/dsdt.asl M src/mainboard/clevo/kbl-u/romstage.c M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb 5 files changed, 20 insertions(+), 54 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/45129/1
diff --git a/src/mainboard/clevo/kbl-u/Kconfig b/src/mainboard/clevo/kbl-u/Kconfig index b0e5353..62b0bf8 100644 --- a/src/mainboard/clevo/kbl-u/Kconfig +++ b/src/mainboard/clevo/kbl-u/Kconfig @@ -4,20 +4,16 @@ def_bool y select SYSTEM_TYPE_LAPTOP select BOARD_ROMSIZE_KB_8192 - select USE_BLOBS - select ADD_FSP_BINARIES - select FSP_USE_REPO - select EC_ACPI +# select EC_ACPI select INTEL_GMA_HAVE_VBT select SOC_INTEL_KABYLAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select MAINBOARD_USES_FSP2_0 select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 - select HAVE_ACPI_RESUME +# select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES # select HAVE_CMOS_DEFAULT - select HAVE_SMI_HANDLER +# select HAVE_SMI_HANDLER
config MAINBOARD_DIR string diff --git a/src/mainboard/clevo/kbl-u/Makefile.inc b/src/mainboard/clevo/kbl-u/Makefile.inc index 50578c2..aa8029d 100644 --- a/src/mainboard/clevo/kbl-u/Makefile.inc +++ b/src/mainboard/clevo/kbl-u/Makefile.inc @@ -1,3 +1 @@ -romstage-y += pei_data.c - -ramstage-y += ramstage.c pei_data.c hda_verb.c +ramstage-y += ramstage.c hda_verb.c diff --git a/src/mainboard/clevo/kbl-u/dsdt.asl b/src/mainboard/clevo/kbl-u/dsdt.asl index 5eb6b04..12c8938 100644 --- a/src/mainboard/clevo/kbl-u/dsdt.asl +++ b/src/mainboard/clevo/kbl-u/dsdt.asl @@ -16,7 +16,7 @@ * GNU General Public License for more details. */
-#include <arch/acpi.h> +#include <acpi/acpi.h> DefinitionBlock( "dsdt.aml", "DSDT", @@ -26,23 +26,4 @@ 0x20110725 // OEM revision ) { - #include "acpi/platform.asl" - - // global NVS and variables - #include <soc/intel/skylake/acpi/globalnvs.asl> - - // CPU - #include <cpu/intel/common/acpi/cpu.asl> - - Scope (_SB) { - Device (PCI0) - { - #include <soc/intel/skylake/acpi/systemagent.asl> - #include <soc/intel/skylake/acpi/pch.asl> - } - - } - - // Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> } diff --git a/src/mainboard/clevo/kbl-u/romstage.c b/src/mainboard/clevo/kbl-u/romstage.c index 101095c..b127a3e 100644 --- a/src/mainboard/clevo/kbl-u/romstage.c +++ b/src/mainboard/clevo/kbl-u/romstage.c @@ -24,6 +24,21 @@ #include <arch/io.h> #include "pei_data.h"
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = {121, 81, 100}; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = {100, 40, 20, 20, 26}; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + + void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg; @@ -37,8 +52,6 @@ dump_spd_info(&blk); assert(blk.spd_array[0][0] != 0);
- mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index 1a552d4..feec0b8 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -29,8 +29,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "1" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" @@ -39,21 +37,12 @@ register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[2]" = "0" register "SataSpeedLimit" = "2" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "1" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s @@ -61,15 +50,6 @@ register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "0"
- register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # Root port #1 x4 (TBT) register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" @@ -125,8 +105,6 @@ register "SendVrMbxCmd" = "2"
- # PL2 override 44W - register "tdp_pl2_override" = "40"
# VR Settings Configuration for 4 Domains #+----------------+-----------+-----------+-------------+----------+
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45129
to look at the new patch set (#2).
Change subject: [NOT FOR MERGE] mb/clevo/n130wu: Make master compiling ......................................................................
[NOT FOR MERGE] mb/clevo/n130wu: Make master compiling
Change-Id: I30b4af7430c4b80d03e9601ef9d81d1624f0be87 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Makefile.inc M src/mainboard/clevo/kbl-u/dsdt.asl M src/mainboard/clevo/kbl-u/romstage.c M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb 5 files changed, 20 insertions(+), 54 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/45129/2
-
Felix Singer (Code Review)