[S] Change in coreboot[master]: soc/amd/stoneyridge: request binaryPI to use \_SB_ scope in PSTATE SSDT

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73385 )

Change subject: soc/amd/stoneyridge: request binaryPI to use _SB_ scope in PSTATE SSDT
......................................................................

soc/amd/stoneyridge: request binaryPI to use _SB_ scope in PSTATE SSDT

Instead of having binaryPI generate a PSTATE SSDT that uses _PR_ as the
scope for the CPU objects and patching this SSDT in coreboot to use the
_SB_ scope in patch_ssdt_processor_scope, request binaryPI to use the
_SB_ scope instead by setting the late platform configuration option
ProcessorScopeInSb to true.

TEST=Careena still boots and Linux doesn't show any ACPI errors with
this patch applied. With only patch_ssdt_processor_scope removed, but
the ProcessorScopeInSb option not set, Linux will complain that it can't
resolve the \PR.P00x symbols.

Signed-off-by: Felix Held 
Change-Id: If88820a0f5df923f129e2e3b5335f5f0e38ee7f5
---
M src/soc/amd/common/pi/agesawrapper.c
M src/soc/amd/stoneyridge/northbridge.c
2 files changed, 24 insertions(+), 16 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/73385/1

diff --git a/src/soc/amd/common/pi/agesawrapper.c b/src/soc/amd/common/pi/agesawrapper.c
index 4085855..07fc16e 100644
--- a/src/soc/amd/common/pi/agesawrapper.c
+++ b/src/soc/amd/common/pi/agesawrapper.c
@@ -266,6 +266,9 @@
    	LateParams->GnbLateConfiguration.FchIoapicId = FCH_IOAPIC_ID;
    }

+	/* Make binariPY use _SB_ as processor object scope in PSTATE SSDT */
+	LateParams->PlatformConfig.ProcessorScopeInSb = true;
+
    timestamp_add_now(TS_AGESA_INIT_LATE_START);
    Status = amd_dispatch(LateParams);
    timestamp_add_now(TS_AGESA_INIT_LATE_END);
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 6389cc4..e318024 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -207,21 +207,6 @@
    acpigen_pop_len();
 }

-static void patch_ssdt_processor_scope(acpi_header_t *ssdt)
-{
-	unsigned int len = ssdt->length - sizeof(acpi_header_t);
-	unsigned int i;
-
-	for (i = sizeof(acpi_header_t); i < len; i++) {
-		/* Search for _PR_ scope and replace it with _SB_ */
-		if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f)
-			*(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f;
-	}
-	/* Recalculate checksum */
-	ssdt->checksum = 0;
-	ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
-}
-
 static unsigned long agesa_write_acpi_tables(const struct device *device,
    				     unsigned long current,
    				     acpi_rsdp_t *rsdp)
@@ -296,7 +281,6 @@
    printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
    ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE);
    if (ssdt != NULL) {
-		patch_ssdt_processor_scope(ssdt);
    	memcpy((void *)current, ssdt, ssdt->length);
    	ssdt = (acpi_header_t *)current;
    	current += ssdt->length;