New patch to review for coreboot: ae068a2 cpu/intel: Add configuration for socket LGA1155
Alexandru Gagniuc (mr.nuke.me@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4623
-gerrit
commit ae068a2762961f820fc4f71eabf34c2ef5615dd7 Author: Alexandru Gagniuc mr.nuke.me@gmail.com Date: Sat Jan 4 22:17:21 2014 -0600
cpu/intel: Add configuration for socket LGA1155
This is not a functional change. It just allows mainboards to explicitly select LGA1155.
Change-Id: If4cf88fffcb3e37e24679fb70ced7c54f68b1837 Signed-off-by: Alexandru Gagniuc mr.nuke.me@gmail.com --- src/cpu/intel/Kconfig | 1 + src/cpu/intel/Makefile.inc | 1 + src/cpu/intel/socket_LGA1155/Kconfig | 27 +++++++++++++++++++++++++++ src/cpu/intel/socket_LGA1155/Makefile.inc | 8 ++++++++ src/cpu/intel/socket_LGA1155/socket_LGA1155.c | 5 +++++ 5 files changed, 42 insertions(+)
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 6f4f561..51c824a 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -32,6 +32,7 @@ source src/cpu/intel/socket_mPGA603/Kconfig source src/cpu/intel/socket_mPGA604/Kconfig source src/cpu/intel/socket_PGA370/Kconfig source src/cpu/intel/socket_441/Kconfig +source src/cpu/intel/socket_LGA1155/Kconfig source src/cpu/intel/socket_LGA771/Kconfig source src/cpu/intel/socket_LGA775/Kconfig source src/cpu/intel/socket_rPGA989/Kconfig diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 964369d..1fbbedb 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -25,6 +25,7 @@ subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA771) += socket_LGA771 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA1155) += socket_LGA1155
#socket_mPGA604_533Mhz #socket_mPGA604_800Mhz diff --git a/src/cpu/intel/socket_LGA1155/Kconfig b/src/cpu/intel/socket_LGA1155/Kconfig new file mode 100644 index 0000000..536f6ec --- /dev/null +++ b/src/cpu/intel/socket_LGA1155/Kconfig @@ -0,0 +1,27 @@ +config CPU_INTEL_SOCKET_LGA1155 + bool + +if CPU_INTEL_SOCKET_LGA1155 + +# Northbridge config automatically selects the appropriate processor model, +# since the CPU and NB come on the same die. However, we select them here +# explicitly for consistency with other socket configs and to document the +# intention. + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y + select MMX + select SSE + select CACHE_AS_RAM + # 2nd Gen Core processors + select CPU_INTEL_MODEL_206AX + select NORTHBRIDGE_INTEL_SANDYBRIDGE + # 3rd Gen Core processors + select CPU_INTEL_MODEL_306AX + select NORTHBRIDGE_INTEL_IVYBRIDGE + +config CACHE_MRC_BIN + bool + default n + +endif # CPU_INTEL_SOCKET_LGA1155 diff --git a/src/cpu/intel/socket_LGA1155/Makefile.inc b/src/cpu/intel/socket_LGA1155/Makefile.inc new file mode 100644 index 0000000..4ff24c9 --- /dev/null +++ b/src/cpu/intel/socket_LGA1155/Makefile.inc @@ -0,0 +1,8 @@ +ramstage-y += socket_LGA1155.c +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../turbo diff --git a/src/cpu/intel/socket_LGA1155/socket_LGA1155.c b/src/cpu/intel/socket_LGA1155/socket_LGA1155.c new file mode 100644 index 0000000..63c925d --- /dev/null +++ b/src/cpu/intel/socket_LGA1155/socket_LGA1155.c @@ -0,0 +1,5 @@ +#include <device/device.h> + +struct chip_operations cpu_intel_socket_LGA1155_ops = { + CHIP_NAME("Socket LGA1155 CPU") +};
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Alexandru Gagniuc