Change in coreboot[master]: mb/google/poppy/variants/nami: Split FP MCU Wake and IRQ GPIOS

[Shelley Chen (Code Review)]

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/29665

Change subject: mb/google/poppy/variants/nami: Split FP MCU Wake and IRQ GPIOS
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mb/google/poppy/variants/nami: Split FP MCU Wake and IRQ GPIOS

We are seeing problems (interrupt storm) with using the same gpio for
FP MCU wake and irq signals.  Reverting back to using separate gpios
for wake and irq until we resolve the issue.

BUG=b:119447525, b:115706071
BRANCH=Nami
TEST=Run powerd_dbus_suspend from kernel and make sure see DUT drop
     into S0ix in the EC console.  Also, unlock from lock screen with
     fingerprint.

Change-Id: Id7987f28526256808b8ed49e66f66298f7cdbcee
Signed-off-by: Shelley Chen 
---
M src/mainboard/google/poppy/variants/nami/devicetree.cb
M src/mainboard/google/poppy/variants/nami/gpio.c
2 files changed, 4 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/29665/1

diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index de00522..49e35b2 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -455,7 +455,7 @@
    			register "hid" = "ACPI_DT_NAMESPACE_HID"
    			register "uid" = "1"
    			register "compat_string" = ""google,cros-ec-spi""
-				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D6_IRQ)"
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)"
    			register "wake" = "GPE0_DW1_06" # GPP_D6
    			device spi 0 on end
    		end # FPMCU
diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c
index f48033a..1288758 100644
--- a/src/mainboard/google/poppy/variants/nami/gpio.c
+++ b/src/mainboard/google/poppy/variants/nami/gpio.c
@@ -421,12 +421,14 @@
    PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
    /* C3  : SML0CLK ==> TOUCHSCREEN_DIS# */
    PAD_CFG_GPO(GPP_C3, 0, DEEP),
+	/* C8  : UART0_RXD ==> FPMCU_INT_L */
+	PAD_CFG_GPI_APIC(GPP_C8, 20K_PU, DEEP),
    /* C9  : UART0_TXD ==> FP_RST_ODL */
    PAD_CFG_GPO(GPP_C9, 1, DEEP),
    /* D5  : ISH_I2C0_SDA ==> FPMCU_BOOT0 */
    PAD_CFG_GPO(GPP_D5, 0, DEEP),
    /* D6  : ISH_I2C0_SCL ==> FPMCU_INT_L */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_D6, 20K_PU, DEEP, LEVEL, INVERT),
+	PAD_CFG_GPI_ACPI_SCI(GPP_D6, NONE, DEEP, INVERT),
    /* D17 : DMIC_CLK1 ==> NC */
    PAD_CFG_NC(GPP_D17),
 };