Change in coreboot[master]: nb/intel/x4x/raminit: DDR3 specific ODT

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19876 )

Change subject: nb/intel/x4x/raminit: DDR3 specific ODT
......................................................................

nb/intel/x4x/raminit: DDR3 specific ODT

Change-Id: Ie32a008ce636b8eee6ed90c364978f7d37f4bfb2
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/x4x/raminit_ddr23.c
1 file changed, 29 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/19876/1

diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index 28e242c..0d09c05 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -1217,7 +1217,7 @@
 static void program_odt(struct sysinfo *s)
 {
    u8 i;
-	u16 odt[16][2] = {
+	u16 ddr2_odt[16][2] = {
    	{ 0x0000, 0x0000 }, // NC_NC
    	{ 0x0000, 0x0001 }, // x8SS_NC
    	{ 0x0000, 0x0011 }, // x8DS_NC
@@ -1236,10 +1236,35 @@
    	{ 0x0101, 0x0404 }, // x16SS_x16SS
    };

+	u16 ddr3_odt[16][2] = {
+		{ 0x0000, 0x0000 }, // NC_NC
+		{ 0x0000, 0x0001 }, // x8SS_NC
+		{ 0x0000, 0x0021 }, // x8DS_NC
+		{ 0x0000, 0x0001 }, // x16SS_NC
+		{ 0x0004, 0x0000 }, // NC_x8SS
+		{ 0x0105, 0x0405 }, // x8SS_x8SS
+		{ 0x0105, 0x4465 }, // x8DS_x8SS
+		{ 0x0105, 0x0405 }, // x16SS_x8SS
+		{ 0x0084, 0x0000 }, // NC_x8DS
+		{ 0x1195, 0x0405 }, // x8SS_x8DS
+		{ 0x1195, 0x4465 }, // x8DS_x8DS
+		{ 0x1195, 0x0405 }, // x16SS_x8DS
+		{ 0x0004, 0x0000 }, // NC_x16SS
+		{ 0x0105, 0x0405 }, // x8SS_x16SS
+		{ 0x0105, 0x4465 }, // x8DS_x16SS
+		{ 0x0105, 0x0405 }, // x16SS_x16SS
+	};
+
    FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
-		MCHBAR16(0x400*i + 0x298) = odt[s->dimm_config[i]][1];
-		MCHBAR16(0x400*i + 0x294) = odt[s->dimm_config[i]][0];
-		MCHBAR16(0x400*i + 0x29c) = (MCHBAR16(0x400*i + 0x29c) & ~0xfff) | 0x66b;
+		if (s->spd_type == DDR2) {
+			MCHBAR16(0x400*i + 0x298) = ddr2_odt[s->dimm_config[i]][1];
+			MCHBAR16(0x400*i + 0x294) = ddr2_odt[s->dimm_config[i]][0];
+		} else {
+			MCHBAR16(0x400*i + 0x298) = ddr3_odt[s->dimm_config[i]][1];
+			MCHBAR16(0x400*i + 0x294) = ddr3_odt[s->dimm_config[i]][0];
+		}
+		MCHBAR16(0x400*i + 0x29c) = (MCHBAR16(0x400*i + 0x29c) & ~0xfff) |
+			(s->spd_type == DDR2 ? 0x66b : 0x778);
    	MCHBAR32(0x400*i + 0x260) = (MCHBAR32(0x400*i + 0x260) & ~0x70e3c00) | 0x3063c00;
    }
 }