New patch to review for coreboot: soc/glk: Add stage cache implementation to improve resume time
Hannah Williams (hannah.williams@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17850
-gerrit
commit 16076a7f4e4d3a0af672f83a1363608115a26c6f Author: Sarkar, Barnali barnali.sarkar@intel.com Date: Tue Dec 13 12:02:55 2016 -0800
soc/glk: Add stage cache implementation to improve resume time
Ported from https://review.coreboot.org/#/c/16833
Change-Id: I712d2d8d3ac38b8217c5d91a04eee596cfdde214 Signed-off-by: Hannah Williams hannah.williams@intel.com --- src/soc/intel/glk/Kconfig | 2 +- src/soc/intel/glk/cpu.c | 8 ++++++-- src/soc/intel/glk/include/soc/smm.h | 4 +--- src/soc/intel/glk/memmap.c | 31 +++++++++++++++++++++++++++++++ src/soc/intel/glk/romstage.c | 15 +++++++++++++++ 5 files changed, 54 insertions(+), 6 deletions(-)
diff --git a/src/soc/intel/glk/Kconfig b/src/soc/intel/glk/Kconfig index 7f936a7..10ad825 100644 --- a/src/soc/intel/glk/Kconfig +++ b/src/soc/intel/glk/Kconfig @@ -25,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_NHLT # Misc options select C_ENVIRONMENT_BOOTBLOCK + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select COLLECT_TIMESTAMPS select COMMON_FADT select GENERIC_GPIO_LIB @@ -33,7 +34,6 @@ config CPU_SPECIFIC_OPTIONS select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE - select NO_STAGE_CACHE select NO_XIP_EARLY_STAGES select PARALLEL_MP select PCIEXP_ASPM diff --git a/src/soc/intel/glk/cpu.c b/src/soc/intel/glk/cpu.c index 7d74c2b..f20e89c 100644 --- a/src/soc/intel/glk/cpu.c +++ b/src/soc/intel/glk/cpu.c @@ -98,19 +98,23 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, { void *smm_base; size_t smm_size; + void *handler_base; + size_t handler_size;
/* All range registers are aligned to 4KiB */ const uint32_t rmask = ~((1 << 12) - 1);
/* Initialize global tracking state. */ smm_region(&smm_base, &smm_size); + smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); + relo_attrs.smbase = (uint32_t)smm_base; relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;
- *perm_smbase = relo_attrs.smbase; - *perm_smsize = smm_size - CONFIG_SMM_RESERVED_SIZE; + *perm_smbase = (uintptr_t)handler_base; + *perm_smsize = handler_size; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); }
diff --git a/src/soc/intel/glk/include/soc/smm.h b/src/soc/intel/glk/include/soc/smm.h index 7a9846e..740d02b 100644 --- a/src/soc/intel/glk/include/soc/smm.h +++ b/src/soc/intel/glk/include/soc/smm.h @@ -20,6 +20,7 @@
#include <stdint.h> #include <soc/gpio.h> +#include <fsp/memmap.h>
/* These helpers are for performing SMM relocation. */ void southbridge_clear_smi_status(void); @@ -35,7 +36,4 @@ void southbridge_smm_enable_smi(void); /* Mainboard handler for GPI SMIs*/ void mainboard_smi_gpi_handler(const struct gpi_status *sts);
-/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); #endif diff --git a/src/soc/intel/glk/memmap.c b/src/soc/intel/glk/memmap.c index ea6f447..85585ce 100644 --- a/src/soc/intel/glk/memmap.c +++ b/src/soc/intel/glk/memmap.c @@ -24,6 +24,7 @@ #define __SIMPLE_DEVICE__
#include <arch/io.h> +#include <assert.h> #include <cbmem.h> #include <device/pci.h> #include <soc/northbridge.h> @@ -52,3 +53,33 @@ void smm_region(void **start, size_t *size) *start = (void *)smm_region_start(); *size = smm_region_size(); } +int smm_subregion(int sub, void **start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + sub_base = smm_region_start(); + sub_size = smm_region_size(); + + assert(sub_size > CONFIG_SMM_RESERVED_SIZE); + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - cache_size; + sub_size = cache_size; + break; + default: + return -1; + } + + *start = (void *)sub_base; + *size = sub_size; + + return 0; +} diff --git a/src/soc/intel/glk/romstage.c b/src/soc/intel/glk/romstage.c index 96c9c0a..61f0278 100644 --- a/src/soc/intel/glk/romstage.c +++ b/src/soc/intel/glk/romstage.c @@ -29,6 +29,7 @@ #include <device/pci_def.h> #include <device/resource.h> #include <fsp/api.h> +#include <fsp/memmap.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/northbridge.h> @@ -105,6 +106,9 @@ asmlinkage void car_stage_entry(void) uintptr_t top_of_ram; bool s3wake; struct chipset_power_state *ps = car_get_var_ptr(&power_state); + void *smm_base; + size_t smm_size; + uintptr_t tseg_base;
timestamp_add_now(TS_START_ROMSTAGE);
@@ -135,6 +139,17 @@ asmlinkage void car_stage_entry(void) postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+ /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uintptr_t)smm_base; + postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + run_postcar_phase(&pcf); }
-
Hannah Williams