Change in coreboot[master]: mb/adlrvp: Fix DDR5 Boot issue

[Meera Ravindranath (Code Review)]

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Subrata Banik.
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50996 )

Change subject: mb/adlrvp: Fix DDR5 Boot issue
......................................................................

Patch Set 12:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/50996/comment/7deefc67_f316e48f 
PS11, Line 9: DDR5 boot flow is currently broken in master coreboot.
> I think it would be better to capture that there are changes required in the smbus driver to accommo […]

Done

File src/mainboard/intel/adlrvp/romstage_fsp_params.c:

https://review.coreboot.org/c/coreboot/+/50996/comment/49765273_ea8ebab5 
PS11, Line 61: for (int i = 0; i < 16; i++)
> Can you please add a comment why this is being done here and a TODO to drop this once the smbus driv […]

Done