Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs

[Werner Zeh (Code Review)]

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Patrick Rudolph.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54959 )

Change subject: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs
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Patch Set 6:

(4 comments)

File src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/54959/comment/ed821cd7_391eacd1 
PS6, Line 75: [PchSerialIoIndexGSPI0] = 1,
            : 		[PchSerialIoIndexGSPI1] = 1,
            : 		[PchSerialIoIndexGSPI2] = 1,
You disable or hide the GSPI-Controllers but still enable their Chip Selct. Is this what you want?

https://review.coreboot.org/c/coreboot/+/54959/comment/e6e1c9de_1ca7fd08 
PS6, Line 87: [PchSerialIoIndexGSPI0] = 0,
            : 		[PchSerialIoIndexGSPI1] = 0,
            : 		[PchSerialIoIndexGSPI2] = 0,
You set the chip select mode to "hardware mode" in SerialIoGSpiCsMode and then set the state to 0? This means that chip select is active all the time. Is this something you really want or have a got it wrong?

File src/soc/intel/elkhartlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/54959/comment/181d6aa4_26ca7832 
PS6, Line 65: 0x1B44AC09;
Since you use constants here: Would you mind to add a comment which describes these values?

https://review.coreboot.org/c/coreboot/+/54959/comment/79359f92_83c3a38e 
PS6, Line 102: params->SerialIoUartCtsPinMuxPolicy[0] = 0x2B01320F;
             : 	params->SerialIoUartRtsPinMuxPolicy[0] = 0x2B01220E;
             : 	params->SerialIoUartRxPinMuxPolicy[0] = 0x2B01020C;
             : 	params->SerialIoUartTxPinMuxPolicy[0] = 0x2B01120D;
A comment describing the values would be nice here.