Change in coreboot[master]: mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge

[Casper Chang (Code Review)]

Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58743 )

Change subject: mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge
......................................................................

mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge

Enable RTD3 driver for PCIe-eMMC bridge.

BUG=b:204469567
TEST=Boot into eMMC storage and perform suspend stress 100 cycle passed

Change-Id: Ice4401a7519303a892b2bb1b440c443ab8221a0a
Signed-off-by: Casper Chang 
---
M src/mainboard/google/brya/variants/primus/gpio.c
M src/mainboard/google/brya/variants/primus/overridetree.cb
2 files changed, 8 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/58743/1

diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c
index ba423fc..8c02d28 100644
--- a/src/mainboard/google/brya/variants/primus/gpio.c
+++ b/src/mainboard/google/brya/variants/primus/gpio.c
@@ -46,8 +46,7 @@
    PAD_NC(GPP_E3, NONE),
    /* E7  : PROC_GP1 ==> NC */
    PAD_NC(GPP_E7, NONE),
-	/* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
-	PAD_CFG_GPO(GPP_E20, 1, DEEP),
+

/* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */
    PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
@@ -108,6 +107,8 @@
    PAD_CFG_GPO(GPP_E16, 0, DEEP),
    /* E15 : RSVD_TP ==> PCH_WP_OD */
    PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
+	PAD_CFG_GPO(GPP_E20, 1, DEEP),
    /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
    PAD_CFG_GPO(GPP_F21, 0, DEEP),
    /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb
index c4debb4..0e6f451 100644
--- a/src/mainboard/google/brya/variants/primus/overridetree.cb
+++ b/src/mainboard/google/brya/variants/primus/overridetree.cb
@@ -119,6 +119,11 @@
    		end
    	end
    	device ref pcie_rp3 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
+				register "srcclk_pin" = "6"
+				device generic 0 on end
+			end
    		# Enable PCIe-to-eMMC bridge PCIE 3 using clk 6
    		register "pch_pcie_rp[PCH_RP(3)]" = "{
    			.clk_src = 6,