[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC

[Name of user not set (Code Review)]

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Singer, Frans Hendriks, Jérémy Compostella, Paul Menzel, Shuo Liu, Vasiliy Khoruzhick.

[e-mail] has posted comments on this change by [e-mail]. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email )

Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
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Patch Set 50:

(4 comments)

File src/soc/intel/snowridge/chip.c:

https://review.coreboot.org/c/coreboot/+/83321/comment/acfedc07_381ffe91?usp... :
PS50, Line 417: 		if (is_dev_on_domain0(dev) && is_pch_slot(PCI_DEV2DEVFN(PCI_BDF(dev))) &&
> Seems that these static PCH devices will be assigned with an ops later by the PCI probing process, r […]

yes, most of them are assigned with `default_pci_ops_dev`.

https://review.coreboot.org/c/coreboot/+/83321/comment/a12188ec_7228b19a?usp... :
PS50, Line 418: 		    (dev->ops == NULL || dev->ops->enable == NULL)) {
> What is the benefit of (dev->ops == NULL || dev->ops->enable == NULL)?, just to double confirm it is […]

Actually at the time when this function is called, the device is not assigned with a device operation, I think it could be removed to avoid confusing.

File src/soc/intel/snowridge/systemagent.c:

https://review.coreboot.org/c/coreboot/+/83321/comment/7a49a27f_858fee12?usp... :
PS15, Line 17: 	*size = CONFIG_ECAM_MMCONF_LENGTH;
> Maybe to add a comment here as a note?

Done

File src/soc/intel/snowridge/systemagent.c:

https://review.coreboot.org/c/coreboot/+/83321/comment/b9888390_dfe29996?usp... :
PS50, Line 31: 	/* The PCIe MMCFG limit in registers is not correct thus using the configuration value here. */
@[e-mail], I've added comment for it in the latest patch.