Change in coreboot[master]: soc/amd/cezanne: remove UART2/3 AOAC device offsets

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50230 )

Change subject: soc/amd/cezanne: remove UART2/3 AOAC device offsets
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soc/amd/cezanne: remove UART2/3 AOAC device offsets

UART2 and UART3 don't exist on Cezanne which now has been verified, so
remove the corresponding AOAC offsets.

Signed-off-by: Felix Held 
Change-Id: I67755bd34df3a835cc39929bdc24f711d158b3a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50230
Tested-by: build bot (Jenkins) 
Reviewed-by: Raul Rangel 
---
M src/soc/amd/cezanne/include/soc/southbridge.h
1 file changed, 0 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Raul Rangel: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index 6949fa5..a38d706 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -22,9 +22,7 @@
 #define FCH_AOAC_DEV_I2C5		10
 #define FCH_AOAC_DEV_UART0		11
 #define FCH_AOAC_DEV_UART1		12
-#define FCH_AOAC_DEV_UART2		16
 #define FCH_AOAC_DEV_AMBA		17
-#define FCH_AOAC_DEV_UART3		26
 #define FCH_AOAC_DEV_ESPI		27

/* IO 0xf0 NCP Error */