[XS] Change in coreboot[main]: mb/starlabs/starlite_adl: Enable TLS Confidentiality GPIO

[Sean Rhodes (Code Review)]

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86066?usp=email )

Change subject: mb/starlabs/starlite_adl: Enable TLS Confidentiality GPIO
......................................................................

mb/starlabs/starlite_adl: Enable TLS Confidentiality GPIO

This board does not have a 20K Pull Down resistor fitted here,
meaning this will not change anything. However, it unifies the
the configuration with the other Star Labs boards.

Change-Id: Iee0adea21c124e0a421a1506310944cc883a73fb
Signed-off-by: Sean Rhodes 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86066
Tested-by: build bot (Jenkins) 
Reviewed-by: Matt DeVillier 
---
M src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Matt DeVillier: Looks good to me, approved

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index dac6896..002d0e5 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -148,7 +148,7 @@
    /* C2:		TLS Confidentiality	Weak Internal PD 20K
    			Low:	Disabled
    			High:	Enabled				*/
-	PAD_CFG_GPO(GPP_C2, 0, DEEP),
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST),
    /* C3:		SML 0 Clock					*/
    PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
    /* C4:		SML 0 Data					*/