Change in coreboot[master]: [Do not merge] soc/intel/alderlake: Enable USB2 port reset message on...

[Anil Kumar K (Code Review)]

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61536 )

Change subject: [Do not merge] soc/intel/alderlake: Enable USB2 port reset message on Type-C ports
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[Do not merge] soc/intel/alderlake: Enable USB2 port reset message on Type-C ports

Change-Id: Iabc6f308992bf3868da66f152c6d7b0164e64bea
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/include/soc/usb.h
2 files changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/61536/1

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 8284980..5695974 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -439,6 +439,9 @@
    		s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
    	else
    		s_cfg->Usb2OverCurrentPin[i] = OC_SKIP;
+
+		if (config->usb2_ports[i].type_c)
+			params->PortResetMessageEnable[i] = 1;
    }

for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
diff --git a/src/soc/intel/alderlake/include/soc/usb.h b/src/soc/intel/alderlake/include/soc/usb.h
index e339c72..70a367e 100644
--- a/src/soc/intel/alderlake/include/soc/usb.h
+++ b/src/soc/intel/alderlake/include/soc/usb.h
@@ -31,6 +31,7 @@
    uint8_t tx_emp_enable;
    uint8_t pre_emp_bias;
    uint8_t pre_emp_bit;
+	uint8_t type_c;
 };

/* USB Overcurrent pins definition */
@@ -112,6 +113,7 @@
    .tx_emp_enable = USB2_PRE_EMP_ON, \
    .pre_emp_bias  = USB2_BIAS_56P3MV, \
    .pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
+	.type_c	       = 1, \
 }

struct usb3_port_config {