Change in coreboot[master]: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28648

Change subject: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank
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nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank

CxDRT1 bit #16 Pre-All to Activate Delay mut be set if any
rank is populated with 8-bank device technology.

Change-Id: Id6c7dccd295e187acfe00a08294010af53b4d0ee
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/i945/raminit.c
1 file changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/28648/1

diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index c259530..b53afac 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -1491,6 +1491,11 @@
    temp_drt |= (sysinfo->trfc) << 10;

/* Pre-All to Activate Delay */
+	for (i = 0; i < 2*DIMM_SOCKETS; i++) {
+		if (sysinfo->banks[i] != 8)
+			continue;
+		temp_drt |= (1 << 16);
+	}
    temp_drt |= (0 << 16);

/* Precharge to Precharge Delay stays at 1 clock */