Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40770 )
Change subject: soc/amd/picasso: Use AMD common SATA driver ......................................................................
soc/amd/picasso: Use AMD common SATA driver
This change enables the use of AMD common block SATA driver for Picasso. Since the common driver provides ACPI device name and PCI device for SATA in SSDT, these are removed from picasso chip.c and sb_pci0_fch.asl.
BUG=b:153858769 TEST=Verified that "STCR" device is correctly reported on trembyle in SSDT.
Change-Id: Icfdcf9f5e08820b565aa9fcdd0cdc7b5c9eadcd5 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/amd/common/block/sata/sata.c M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/chip.c 3 files changed, 4 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/40770/1
diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c index 2dd0d42..4db00b1 100644 --- a/src/soc/amd/common/block/sata/sata.c +++ b/src/soc/amd/common/block/sata/sata.c @@ -26,6 +26,10 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_CZ_SATA, PCI_DEVICE_ID_AMD_CZ_SATA_AHCI, + PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER0, + PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER1, + PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0, + PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER1, 0 };
diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 3e6029e..04e72c0 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -23,11 +23,6 @@
/* Describe the Southbridge devices */
-/* 0:11.0 - SATA */ -Device(STCR) { - Name(_ADR, 0x00110000) -} /* end STCR */ - /* 0:14.0 - SMBUS */ Device(SBUS) { Name(_ADR, 0x00140000) diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 4b25b88..201afb4 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -65,8 +65,6 @@ return "AZHD"; case LPC_DEVFN: return "LPCB"; - case SATA_DEVFN: - return "STCR"; case SMBUS_DEVFN: return "SBUS"; case XHCI0_DEVFN:
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40770 )
Change subject: soc/amd/picasso: Use AMD common SATA driver ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40770 )
Change subject: soc/amd/picasso: Use AMD common SATA driver ......................................................................
Patch Set 2: Code-Review+2
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40770 )
Change subject: soc/amd/picasso: Use AMD common SATA driver ......................................................................
soc/amd/picasso: Use AMD common SATA driver
This change enables the use of AMD common block SATA driver for Picasso. Since the common driver provides ACPI device name and PCI device for SATA in SSDT, these are removed from picasso chip.c and sb_pci0_fch.asl.
BUG=b:153858769 TEST=Verified that "STCR" device is correctly reported on trembyle in SSDT.
Change-Id: Icfdcf9f5e08820b565aa9fcdd0cdc7b5c9eadcd5 Signed-off-by: Furquan Shaikh furquan@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/40770 Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/common/block/sata/sata.c M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/chip.c 3 files changed, 4 insertions(+), 7 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c index 2dd0d42..4db00b1 100644 --- a/src/soc/amd/common/block/sata/sata.c +++ b/src/soc/amd/common/block/sata/sata.c @@ -26,6 +26,10 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_CZ_SATA, PCI_DEVICE_ID_AMD_CZ_SATA_AHCI, + PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER0, + PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER1, + PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0, + PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER1, 0 };
diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 3e6029e..04e72c0 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -23,11 +23,6 @@
/* Describe the Southbridge devices */
-/* 0:11.0 - SATA */ -Device(STCR) { - Name(_ADR, 0x00110000) -} /* end STCR */ - /* 0:14.0 - SMBUS */ Device(SBUS) { Name(_ADR, 0x00140000) diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 4b25b88..201afb4 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -65,8 +65,6 @@ return "AZHD"; case LPC_DEVFN: return "LPCB"; - case SATA_DEVFN: - return "STCR"; case SMBUS_DEVFN: return "SBUS"; case XHCI0_DEVFN:
-
Aaron Durbin (Code Review) -
Angel Pons (Code Review)
-
Furquan Shaikh (Code Review)