Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Kyösti Mälkki, Fred Reitberger.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74314 )
Change subject: soc/amd: Clarify ACPI _PRT entry generation ......................................................................
Patch Set 2: Code-Review+2
(2 comments)
File src/soc/amd/common/block/pci/acpi_prt.c:
https://review.coreboot.org/c/coreboot/+/74314/comment/9fbfb4b6_986e1b73 PS2, Line 10: /* GNB IO-APIC is located after the FCH IO-APIC */ the existing comment works, but i'd reword this a bit; maybe something like: "The FCH IOAPIC is the first IOAPIC in the system, so the GNB IOAPIC's IRQ numbers start right after the FCH IOAPIC's IRQs" if you think that it should be kept like it was before, feel free to just ACK this comment
https://review.coreboot.org/c/coreboot/+/74314/comment/68a854c1_99abd8bb PS2, Line 11: #define FCH_IOAPIC_INTERRUPTS 24 out of scope for this patch, but i wonder if would it make sense to use ioapic_get_max_vectors(VIO_APIC_VADDR) instead of the hardcoded value of 24. it'll be 24 for all fch ioapics though, so it's not really necessary
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Felix Held (Code Review)