Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili... - coreboot-gerrit

9 Jan 2021


      Attention is currently required from: Tim Crawford, Jeremy Soller.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 )
Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit
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Patch Set 10:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49104/comment/d33300b4_d3434245 
PS10, Line 7: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit
...
This is a bit too long. How about […]
FSP-S*
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e
Gerrit-Change-Number: 49104
Gerrit-PatchSet: 10
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