Change in coreboot[master]: mainboard: Add ASRock G41C-GS

[Arthur Heymans (Code Review)]

Hello Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change.  Please visit

https://review.coreboot.org/18993

to look at the new patch set (#5).

Change subject: mainboard: Add ASRock G41C-GS
......................................................................

mainboard: Add ASRock G41C-GS

Start-point is Gigabyte GA-G41M-ES2L.

This board features a G41 northbridge and an ICH7 southbridge. This
board has slots for both DDR2 and DDR3 (cannot run concurrently
though) but only DDR2 is implemented in coreboot. The SPI flash
resides in a DIP-8 socket.

Tested and working:
* DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky
  with assymetric dimm setups);
* 3,5" IDE;
* SATA;
* PCIe x16 (with some patches up for review);
* Uart, PS2 Keyboard;
* USB, ethernet, audio;
* Native graphic init;
* Fan control;
* Reboot, poweroff;
* Flashrom (vendor and coreboot).

Tested but fails:
* Raminit on resume from S3 (fails on quick_ram_check);
* DDR3 (not implemented in coreboot).

Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0.

Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc
Signed-off-by: Arthur Heymans 
---
A src/mainboard/asrock/g41c-gs/Kconfig
A src/mainboard/asrock/g41c-gs/Kconfig.name
A src/mainboard/asrock/g41c-gs/Makefile.inc
A src/mainboard/asrock/g41c-gs/acpi/ec.asl
A src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl
A src/mainboard/asrock/g41c-gs/acpi/platform.asl
A src/mainboard/asrock/g41c-gs/acpi/superio.asl
A src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl
A src/mainboard/asrock/g41c-gs/acpi_tables.c
A src/mainboard/asrock/g41c-gs/board_info.txt
A src/mainboard/asrock/g41c-gs/cmos.default
A src/mainboard/asrock/g41c-gs/cmos.layout
A src/mainboard/asrock/g41c-gs/cstates.c
A src/mainboard/asrock/g41c-gs/devicetree.cb
A src/mainboard/asrock/g41c-gs/dsdt.asl
A src/mainboard/asrock/g41c-gs/gpio.c
A src/mainboard/asrock/g41c-gs/hda_verb.c
A src/mainboard/asrock/g41c-gs/romstage.c
18 files changed, 911 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/18993/5