Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42655 )
Change subject: sb/intel/i82801jx: Drop `p_cnt_throttling_supported` ......................................................................
sb/intel/i82801jx: Drop `p_cnt_throttling_supported`
The three mainboards using this southbridge do not support it.
Change-Id: I006f1ec26c40f7e2dfc2ddedb017278455368bb9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/i82801jx/chip.h M src/southbridge/intel/i82801jx/fadt.c 2 files changed, 1 insertion(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/42655/1
diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index 3c92da95..028d5c8 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -49,7 +49,6 @@ int c5_enable : 1; int c6_enable : 1; int c3_latency; - int p_cnt_throttling_supported:1; int docking_supported:1;
int throttle_duty : 3; diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c index 7d025b7..9d86b19 100644 --- a/src/southbridge/intel/i82801jx/fadt.c +++ b/src/southbridge/intel/i82801jx/fadt.c @@ -46,10 +46,7 @@ fadt->flush_size = 0; fadt->flush_stride = 0; fadt->duty_offset = 1; - if (chip->p_cnt_throttling_supported) - fadt->duty_width = 3; - else - fadt->duty_width = 0; + fadt->duty_width = 0; fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x32;
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42655 )
Change subject: sb/intel/i82801jx: Drop `p_cnt_throttling_supported` ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42655 )
Change subject: sb/intel/i82801jx: Drop `p_cnt_throttling_supported` ......................................................................
sb/intel/i82801jx: Drop `p_cnt_throttling_supported`
The three mainboards using this southbridge do not support it.
Change-Id: I006f1ec26c40f7e2dfc2ddedb017278455368bb9 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42655 Reviewed-by: Patrick Rudolph siro@das-labor.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/intel/i82801jx/chip.h M src/southbridge/intel/i82801jx/fadt.c 2 files changed, 1 insertion(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index 3c92da95..028d5c8 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -49,7 +49,6 @@ int c5_enable : 1; int c6_enable : 1; int c3_latency; - int p_cnt_throttling_supported:1; int docking_supported:1;
int throttle_duty : 3; diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c index e54ecd9..c0a9d53 100644 --- a/src/southbridge/intel/i82801jx/fadt.c +++ b/src/southbridge/intel/i82801jx/fadt.c @@ -46,10 +46,7 @@ fadt->flush_size = 0; fadt->flush_stride = 0; fadt->duty_offset = 1; - if (chip->p_cnt_throttling_supported) - fadt->duty_width = 3; - else - fadt->duty_width = 0; + fadt->duty_width = 0; fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x32;