Name of user not set #1002424 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33162
Change subject: Add option to disable CPU AES ......................................................................
Add option to disable CPU AES
Added an option(CPU_DISABLE_HW_AES) to cpu/Kconfig to allow to disable CPU hardware-accelerated AES.
For Intel CPUs, this is named "AES-NI", and it's controlled via a Model Specific Register(MSR) called MSR_FEATURE_CONFIG. I have modified some Intel CPU's code to disable AES-NI if that Kconfig option is checked in.
Change-Id: I61da765b4c6efc73b2379c075c3ab46d16764dc4 Signed-off-by: Vladocb vladocb@protonmail.com --- M src/cpu/Kconfig M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/finalize.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/soc/intel/apollolake/cpu.c 6 files changed, 55 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33162/1
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 6078022..5d5b338 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -223,3 +223,10 @@ microcode binary files to include, separated by spaces.
If unsure, leave this blank. + +config CPU_DISABLE_HW_AES + bool "Disable CPU hardware-accelerated AES cryptographic instructions" + default n + help + Check this in to disable AES cryptographic hardware acceleration on the CPU. + diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c index efa8693..e923e50 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c @@ -56,16 +56,26 @@ msr.lo = 0; msr.hi = 0; wrmsr(IA32_THERM_INTERRUPT, msr); + + /* AES_NI */ +#if CONFIG(CPU_DISABLE_HW_AES) + /* disable AES-NI, and lock feature bit using mask 11b=0x3 */ + msr.lo = 0x3u; + msr.hi = 0x0u; + wrmsr(MSR_FEATURE_CONFIG, msr); +#else + /* enable AES-NI */ + msr_set_bit(MSR_FEATURE_CONFIG, 0); +#endif }
static void configure_mca(void) { msr_t msr; - int i;
- msr.lo = msr.hi = 0; + msr.lo = msr.hi = 0x0u; /* This should only be done on a cold boot */ - for (i = 0; i < 6; i++) + for (int i = 0; i < 6; i++) wrmsr(IA32_MC0_STATUS + (i * 4), msr); }
diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index cc2d1a4..3a18eda 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -51,8 +51,16 @@ msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */ - if (cpuid_ecx(1) & (1 << 25)) + if (cpuid_ecx(1) & (1 << 25)) { +#if CONFIG(CPU_DISABLE_HW_AES) + /* disable AES-NI, and lock feature bit using mask 11b=0x3 */ + const msr_t myMsr = { 0x3u, 0x0u }; + wrmsr(MSR_FEATURE_CONFIG, myMsr); +#else + /* keep AES-NI enabled */ msr_set_bit(MSR_FEATURE_CONFIG, 0); +#endif + }
#ifdef LOCK_POWER_CONTROL_REGISTERS /* diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index 5b85601..ced5ee3 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -49,8 +49,15 @@ msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */ - if (cpuid_ecx(1) & (1 << 25)) + if (cpuid_ecx(1) & (1 << 25)) { +#if CONFIG(CPU_DISABLE_HW_AES) + /* disable AES-NI, and lock feature bit using mask 11b=0x3 */ + const msr_t myMsr = { 0x3u, 0x0u }; + wrmsr(MSR_FEATURE_CONFIG, myMsr); +#else msr_set_bit(MSR_FEATURE_CONFIG, 0); +#endif + }
/* Lock TM interrupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 30b00bb..0e370b7 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -49,8 +49,16 @@ msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */ - if (cpuid_ecx(1) & (1 << 25)) + if (cpuid_ecx(1) & (1 << 25)) { +#if CONFIG(CPU_DISABLE_HW_AES) + /* disable AES-NI, and lock feature bit using mask 11b=0x3 */ + const msr_t myMsr = { 0x3u, 0x0u }; + wrmsr(MSR_FEATURE_CONFIG, myMsr); +#else + /* keep AES-NI enabled */ msr_set_bit(MSR_FEATURE_CONFIG, 0); +#endif + }
#ifdef LOCK_POWER_CONTROL_REGISTERS /* diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index aad0f6b..96f9d9f 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -60,12 +60,21 @@ #endif /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0), +#if CONFIG(CPU_DISABLE_HW_AES) + /* + * Disable and Lock the Advanced Encryption Standard (AES-NI) + * feature register + */ + REG_MSR_RMW(MSR_FEATURE_CONFIG, FEATURE_CONFIG_RESERVED_MASK, + FEATURE_CONFIG_LOCK), +#else /* * Enable and Lock the Advanced Encryption Standard (AES-NI) * feature register */ REG_MSR_RMW(MSR_FEATURE_CONFIG, ~FEATURE_CONFIG_RESERVED_MASK, FEATURE_CONFIG_LOCK), +#endif REG_SCRIPT_END };
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I'd like you to reexamine a change. Please visit
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Change subject: Add option to disable CPU AES ......................................................................
Add option to disable CPU AES
Added an option(CPU_DISABLE_HW_AES) to cpu/Kconfig to allow to disable CPU hardware-accelerated AES.
For Intel CPUs, this is named "AES-NI", and it's controlled via a Model Specific Register(MSR) called MSR_FEATURE_CONFIG. I have modified some Intel CPU's code to disable AES-NI if that Kconfig option is checked in.
Change-Id: I61da765b4c6efc73b2379c075c3ab46d16764dc4 Signed-off-by: Vlado CB vladocb@protonmail.com --- M src/cpu/Kconfig M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/finalize.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/soc/intel/apollolake/cpu.c 6 files changed, 55 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33162/2
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I'd like you to reexamine a change. Please visit
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Change subject: Add option to disable CPU AES ......................................................................
Add option to disable CPU AES
Added an option(CPU_DISABLE_HW_AES) to cpu/Kconfig to allow to disable CPU hardware-accelerated AES.
For Intel CPUs, this is named "AES-NI", and it's controlled via a Model Specific Register(MSR) called MSR_FEATURE_CONFIG. I have modified some Intel CPU's code to disable AES-NI if that Kconfig option is checked in.
Change-Id: I61da765b4c6efc73b2379c075c3ab46d16764dc4 Signed-off-by: Vlado CB vladocb@protonmail.com --- M src/cpu/Kconfig M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/finalize.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/soc/intel/apollolake/cpu.c 6 files changed, 54 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33162/3
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I'd like you to reexamine a change. Please visit
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Change subject: Add option to disable CPU AES ......................................................................
Add option to disable CPU AES
Added an option(CPU_DISABLE_HW_AES) to cpu/Kconfig to allow to disable CPU hardware-accelerated AES.
For Intel CPUs, this is named "AES-NI", and it's controlled via a Model Specific Register(MSR) called MSR_FEATURE_CONFIG. I have modified some Intel CPU's code to disable AES-NI if that Kconfig option is checked in.
Change-Id: I61da765b4c6efc73b2379c075c3ab46d16764dc4 Signed-off-by: Vlado CB vladocb@protonmail.com --- M src/cpu/Kconfig M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/finalize.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/soc/intel/apollolake/cpu.c 6 files changed, 55 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33162/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33162 )
Change subject: Add option to disable CPU AES ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/33162/4/src/cpu/Kconfig File src/cpu/Kconfig:
https://review.coreboot.org/#/c/33162/4/src/cpu/Kconfig@232 PS4, Line 232: trailing whitespace
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I'd like you to reexamine a change. Please visit
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Change subject: Add option to disable CPU AES ......................................................................
Add option to disable CPU AES
Added an option(CPU_DISABLE_HW_AES) to cpu/Kconfig to allow to disable CPU hardware-accelerated AES.
For Intel CPUs, this is named "AES-NI", and it's controlled via a Model Specific Register(MSR) called MSR_FEATURE_CONFIG. I have modified some Intel CPU's code to disable AES-NI if that Kconfig option is checked in.
Change-Id: I61da765b4c6efc73b2379c075c3ab46d16764dc4 Signed-off-by: Vlado CB vladocb@protonmail.com --- M src/cpu/Kconfig M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/finalize.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/soc/intel/apollolake/cpu.c 6 files changed, 54 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33162/5
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I'd like you to reexamine a change. Please visit
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Change subject: Add option to disable CPU AES ......................................................................
Add option to disable CPU AES
Added an option(CPU_DISABLE_HW_AES) to cpu/Kconfig to allow to disable CPU hardware-accelerated AES.
For Intel CPUs, this is named "AES-NI", and it's controlled via a Model Specific Register(MSR) called MSR_FEATURE_CONFIG. I have modified some Intel CPU's code to disable AES-NI if that Kconfig option is checked in.
Change-Id: I61da765b4c6efc73b2379c075c3ab46d16764dc4 Signed-off-by: Vlado CB vladocb@protonmail.com --- M src/cpu/Kconfig M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/finalize.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/soc/intel/apollolake/cpu.c 6 files changed, 58 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33162/6
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I'd like you to reexamine a change. Please visit
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Change subject: cpu: Add option to disable CPU AES ......................................................................
cpu: Add option to disable CPU AES
Added an option(CPU_DISABLE_HW_AES) to cpu/Kconfig to allow to disable CPU hardware-accelerated AES.
For Intel CPUs, this is named "AES-NI", and it's controlled via a Model Specific Register(MSR) called MSR_FEATURE_CONFIG. I have modified some Intel CPU's code to disable AES-NI if that Kconfig option is checked in.
Change-Id: I61da765b4c6efc73b2379c075c3ab46d16764dc4 Signed-off-by: Vlado CB vladocb@protonmail.com --- M src/cpu/Kconfig M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/finalize.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/soc/intel/apollolake/cpu.c 6 files changed, 58 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33162/7
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33162 )
Change subject: cpu: Add option to disable CPU AES ......................................................................
Patch Set 7:
(5 comments)
https://review.coreboot.org/#/c/33162/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33162/7//COMMIT_MSG@9 PS7, Line 9: option(CPU_DISABLE_HW_AES) Please add a space before the (.
https://review.coreboot.org/#/c/33162/7//COMMIT_MSG@9 PS7, Line 9: Added Present tense: Add
https://review.coreboot.org/#/c/33162/7//COMMIT_MSG@13 PS7, Line 13: Register(MSR) Please add a space before (.
https://review.coreboot.org/#/c/33162/7//COMMIT_MSG@15 PS7, Line 15: Please add the motivation, why CPU AES should be disabled.
https://review.coreboot.org/#/c/33162/7/src/cpu/Kconfig File src/cpu/Kconfig:
https://review.coreboot.org/#/c/33162/7/src/cpu/Kconfig@231 PS7, Line 231: Check this in to disable AES cryptographic hardware acceleration on the CPU. Please check the indentation (see above).
Please explain to the user, why this would be useful.
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I'd like you to reexamine a change. Please visit
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Change subject: cpu: Add option to disable CPU AES ......................................................................
cpu: Add option to disable CPU AES
Added an option(CPU_DISABLE_HW_AES) to cpu/Kconfig to allow to disable CPU hardware-accelerated AES.
For Intel CPUs, this is named "AES-NI", and it's controlled via a Model Specific Register(MSR) called MSR_FEATURE_CONFIG. I have modified some Intel CPU's code to disable AES-NI if that Kconfig option is checked in.
Change-Id: I61da765b4c6efc73b2379c075c3ab46d16764dc4 Signed-off-by: Vlado CB vladocb@protonmail.com --- M src/cpu/Kconfig M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/finalize.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/soc/intel/apollolake/cpu.c 6 files changed, 71 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33162/8
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33162 )
Change subject: cpu: Add option to disable CPU AES ......................................................................
Patch Set 8:
(6 comments)
https://review.coreboot.org/#/c/33162/8/src/cpu/Kconfig File src/cpu/Kconfig:
https://review.coreboot.org/#/c/33162/8/src/cpu/Kconfig@235 PS8, Line 235: code, you cannot be sure industrial or goverment's backdoors are silently trailing whitespace
https://review.coreboot.org/#/c/33162/8/src/cpu/Kconfig@239 PS8, Line 239: This is a serious risk for military or mission-critical devices. trailing whitespace
https://review.coreboot.org/#/c/33162/8/src/cpu/Kconfig@240 PS8, Line 240: trailing whitespace
https://review.coreboot.org/#/c/33162/8/src/cpu/Kconfig@241 PS8, Line 241: So, as hardware-accelerated AES are THE PERFECT location where to place a backdoor or trailing whitespace
https://review.coreboot.org/#/c/33162/8/src/cpu/Kconfig@242 PS8, Line 242: function hook to steal your keys, and many password managers/cryptography apps & libs trailing whitespace
https://review.coreboot.org/#/c/33162/8/src/cpu/Kconfig@243 PS8, Line 243: seem not to let the user to avoid AES, this option is a good way to mitigate the trailing whitespace
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I'd like you to reexamine a change. Please visit
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Change subject: cpu: Add option to disable CPU AES ......................................................................
cpu: Add option to disable CPU AES
Added an option(CPU_DISABLE_HW_AES) to cpu/Kconfig to allow to disable CPU hardware-accelerated AES.
For Intel CPUs, this is named "AES-NI", and it's controlled via a Model Specific Register(MSR) called MSR_FEATURE_CONFIG. I have modified some Intel CPU's code to disable AES-NI if that Kconfig option is checked in.
Change-Id: I61da765b4c6efc73b2379c075c3ab46d16764dc4 Signed-off-by: Vlado CB vladocb@protonmail.com --- M src/cpu/Kconfig M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/finalize.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/soc/intel/apollolake/cpu.c 6 files changed, 71 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33162/9
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#10).
Change subject: cpu: Add option to disable CPU AES ......................................................................
cpu: Add option to disable CPU AES
Hardware-accelerated AES instructions are a security risk. Hackers can track those instructions very easily and place a function hook just a few lines before they are executed to steal all your passwords & keys.
Also, they represent a problem for many computers having highly-privileged binary blobs: they could use them to perform industrial or government espionage.
So I have added an option CPU_DISABLE_HW_AES to cpu/Kconfig to allow to disable CPU hardware-accelerated AES instructions.
For Intel CPUs, this is named "AES-NI", and it's controlled via a Model Specific Register called MSR_FEATURE_CONFIG. I have modified some Intel CPU's code to disable AES-NI if that Kconfig option is checked in.
Change-Id: I61da765b4c6efc73b2379c075c3ab46d16764dc4 Signed-off-by: Vlado CB vladocb@protonmail.com --- M src/cpu/Kconfig M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/finalize.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/soc/intel/apollolake/cpu.c 6 files changed, 71 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33162/10
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#11).
Change subject: cpu: Add option to disable CPU AES ......................................................................
cpu: Add option to disable CPU AES
Hardware-accelerated AES instructions are a security risk. Hackers can track those instructions very easily and place a function hook just a few lines before they are executed to steal all your passwords & keys.
Also, they represent a problem for many computers having highly-privileged binary blobs: they could use them to perform industrial or government espionage.
So I have added an option CPU_DISABLE_HW_AES to cpu/Kconfig to allow to disable CPU hardware-accelerated AES instructions.
For Intel CPUs, this is named "AES-NI", and it's controlled via a Model Specific Register called MSR_FEATURE_CONFIG. I have modified some Intel CPU's code to disable AES-NI if that Kconfig option is checked in. However, I've found a small problem with that: using hyper-threading, seems some cores still have the AES flags enabled... not sure how to fix that.
Change-Id: I61da765b4c6efc73b2379c075c3ab46d16764dc4 Signed-off-by: Vlado CB vladocb@protonmail.com --- M src/cpu/Kconfig M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/finalize.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/soc/intel/apollolake/cpu.c 6 files changed, 71 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33162/11
Vlado CB has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33162 )
Change subject: cpu: Add option to disable CPU AES ......................................................................
Patch Set 11:
Patch Set 7:
(5 comments)
Thanks for your comments. I've fixed it, more or less. But now I have another problem: enabling hyper-threading seems some cores still have the AES flags enabled... I think the smm_finalize function is only called for "real" cores and not for the sibling ones 8(
Vlado CB has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33162 )
Change subject: cpu: Add option to disable CPU AES ......................................................................
Patch Set 11:
This change is ready for review.
Vlado CB has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33162 )
Change subject: cpu: Add option to disable CPU AES ......................................................................
Patch Set 11:
aban
Vlado CB has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33162 )
Change subject: cpu: Add option to disable CPU AES ......................................................................
Patch Set 11:
This change is ready for review.
Vlado CB has removed a vote on this change.
Change subject: cpu: Add option to disable CPU AES ......................................................................
Removed Verified+1 by build bot (Jenkins) no-reply@coreboot.org
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#12).
Change subject: cpu: Add option to disable CPU AES ......................................................................
cpu: Add option to disable CPU AES
Hardware-accelerated AES instructions are a security risk. Hackers can track those instructions very easily and place a function hook just a few lines before they are executed to steal all your passwords & keys.
Also, they represent a problem for many computers having highly-privileged binary blobs: they could use them to perform industrial or government espionage.
So I have added an option CPU_DISABLE_HW_AES to cpu/Kconfig to allow to disable CPU hardware-accelerated AES instructions.
For Intel CPUs, this is named "AES-NI", and it's controlled via a Model Specific Register called MSR_FEATURE_CONFIG. I have modified some Intel CPU's code to disable AES-NI if that Kconfig option is checked in. However, I've found a small problem with that: using hyper-threading, seems some cores still have the AES flags enabled... not sure how to fix that.
Change-Id: I61da765b4c6efc73b2379c075c3ab46d16764dc4 Signed-off-by: Vlado CB vladocb@protonmail.com --- M src/cpu/Kconfig M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/finalize.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/soc/intel/apollolake/cpu.c 6 files changed, 58 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33162/12
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#13).
Change subject: cpu: Add option to disable CPU AES ......................................................................
cpu: Add option to disable CPU AES
Change-Id: I61da765b4c6efc73b2379c075c3ab46d16764dc4 --- M src/cpu/Kconfig M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/finalize.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/soc/intel/apollolake/cpu.c 6 files changed, 58 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33162/13
Vlado CB has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/33162 )
Change subject: cpu: Add option to disable CPU AES ......................................................................
Abandoned
need rework
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