Uwe Poeche has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34173 )
Change subject: siemens/mc_bdx1: increase SPI-flash erase timeout ......................................................................
siemens/mc_bdx1: increase SPI-flash erase timeout
This patch provides an increased timeout (60ms ->200ms) for SPI HW-sequencing flash erase operations. Without that the erase for MRC cache writing on siemens/mc_bdx1 sometimes goes wrong because the timeout stops waiting for flash cycle completion. It was found during continuous integration. Investigation showed that the used flash type takes sporadic (e.g.5% of the test cycles) more time for completion of erasing operation if the ambient temperature increases. The measured time values are in range of data sheet of SPI flash. 60ms is a typical value. So increasing the value is necessary.
tested on siemens/bdx1; measured time values with increased ambient temperature of flash were always smaller than worst case value of 200ms.
Change-Id: Id50636f9ed834ffd7810946798b300e58b2c14d2 Signed-off-by: Uwe Poeche uwe.poeche@siemens.com --- M src/southbridge/intel/common/spi.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/34173/1
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 8430dc8..e3ba53d 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -727,7 +727,7 @@ u32 start, end, erase_size; int ret; uint16_t hsfc; - uint16_t timeout = 1000 * 60; + uint32_t timeout = 1000 * 200;
erase_size = flash->sector_size; if (offset % erase_size || len % erase_size) {
Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34173 )
Change subject: siemens/mc_bdx1: increase SPI-flash erase timeout ......................................................................
Patch Set 1: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/34173/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34173/1//COMMIT_MSG@7 PS1, Line 7: i Please start with a upper case letter
https://review.coreboot.org/c/coreboot/+/34173/1//COMMIT_MSG@14 PS1, Line 14: operation if the that is more than 80 columns
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34173 )
Change subject: siemens/mc_bdx1: increase SPI-flash erase timeout ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34173/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34173/1//COMMIT_MSG@1 PS1, Line 1: Parent: cb587a25 (drivers/intel: Move FSP stage_cache implementation into common block) This is not just mc_bdx1 related but hits the overall common SPI-driver. PLease adjust the commit message.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34173 )
Change subject: siemens/mc_bdx1: increase SPI-flash erase timeout ......................................................................
Patch Set 1:
And maybe we can synchronise this timeout with the define used for the SW-sequence. SW-sequence uses 200 ms as well already.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34173 )
Change subject: siemens/mc_bdx1: increase SPI-flash erase timeout ......................................................................
Patch Set 1:
(1 comment)
Should the time-outs be unified?
https://review.coreboot.org/c/coreboot/+/34173/1/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/34173/1/src/southbridge/intel/commo... PS1, Line 730: uint32_t timeout = 1000 * 200; The function signature takes an unsigned integer.
src/southbridge/intel/common/spi.c:static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
Uwe Poeche has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34173 )
Change subject: siemens/mc_bdx1: increase SPI-flash erase timeout ......................................................................
Patch Set 1:
Patch Set 1:
(1 comment)
Should the time-outs be unified?
Between unified? We could unify the timeouts between SW- and HW-sequencing. SW-sequencing uses timeout from src/drivers/spi/spi_flash_internal.h.
Hello Werner Zeh, Patrick Rudolph, Felix Held, Mario Scheithauer, David Hendricks, Paul Menzel, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34173
to look at the new patch set (#2).
Change subject: southbridge/intel/common/spi.c: Increase SPI-flash erase timeout ......................................................................
southbridge/intel/common/spi.c: Increase SPI-flash erase timeout
This patch provides an increased timeout (60ms ->200ms) for SPI HW-sequencing flash erase operations. Without that the erase for MRC cache writing on siemens/mc_bdx1 sometimes goes wrong because the timeout stops waiting for flash cycle completion. It was found during continuous integration. Investigation showed that the used flash type takes sporadic (e.g.5% of the test cycles) more time for completion of erasing operation if the ambient temperature increases. The measured time values are in range of data sheet of SPI flash. 60ms is a typical value. So increasing the value is necessary.
tested on siemens/bdx1; measured time values with increased ambient temperature of flash were always smaller than worst case value of 200ms.
Change-Id: Id50636f9ed834ffd7810946798b300e58b2c14d2 Signed-off-by: Uwe Poeche uwe.poeche@siemens.com --- M src/southbridge/intel/common/spi.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/34173/2
Hello Werner Zeh, Patrick Rudolph, Felix Held, Mario Scheithauer, David Hendricks, Paul Menzel, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34173
to look at the new patch set (#3).
Change subject: southbridge/intel/common/spi.c: Increase SPI-flash erase timeout ......................................................................
southbridge/intel/common/spi.c: Increase SPI-flash erase timeout
This patch provides an increased timeout (60ms ->200ms) for SPI HW-sequencing flash erase operations. Without that the erase for MRC cache writing on siemens/mc_bdx1 sometimes goes wrong because the timeout stops waiting for flash cycle completion. It was found during continuous integration. Investigation showed that the used flash type takes sporadic (e.g.5% of the test cycles) more time for completion of erasing operation if the ambient temperature increases. The measured time values are in range of data sheet of SPI flash. 60ms is a typical value. So increasing the value is necessary.
tested on siemens/bdx1; measured time values with increased ambient temperature of flash were always smaller than worst case value of 200ms.
Change-Id: Id50636f9ed834ffd7810946798b300e58b2c14d2 Signed-off-by: Uwe Poeche uwe.poeche@siemens.com --- M src/southbridge/intel/common/spi.c 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/34173/3
Uwe Poeche has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34173 )
Change subject: southbridge/intel/common/spi.c: Increase SPI-flash erase timeout ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34173/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34173/1//COMMIT_MSG@1 PS1, Line 1: Parent: cb587a25 (drivers/intel: Move FSP stage_cache implementation into common block)
This is not just mc_bdx1 related but hits the overall common SPI-driver. […]
Done
https://review.coreboot.org/c/coreboot/+/34173/1//COMMIT_MSG@7 PS1, Line 7: i
Please start with a upper case letter
Done
https://review.coreboot.org/c/coreboot/+/34173/1//COMMIT_MSG@14 PS1, Line 14: operation if the
that is more than 80 columns
Done
https://review.coreboot.org/c/coreboot/+/34173/1/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/34173/1/src/southbridge/intel/commo... PS1, Line 730: uint32_t timeout = 1000 * 200;
The function signature takes an unsigned integer. […]
Done
Hello Werner Zeh, Patrick Rudolph, Felix Held, Mario Scheithauer, David Hendricks, Paul Menzel, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34173
to look at the new patch set (#4).
Change subject: southbridge/intel/common/spi.c: Increase SPI-flash erase timeout ......................................................................
southbridge/intel/common/spi.c: Increase SPI-flash erase timeout
This patch provides an increased timeout (60ms ->200ms) for SPI HW-sequencing flash erase operations. Without that the erase for MRC cache writing on siemens/mc_bdx1 sometimes goes wrong because the timeout stops waiting for flash cycle completion. It was found during continuous integration. Investigation showed that the used flash type takes sporadic (e.g.5% of the test cycles) more time for completion of erasing operation if the ambient temperature increases. The measured time values are in range of data sheet of SPI flash. 60ms is a typical value. So increasing the value is necessary.
tested on siemens/bdx1; measured time values with increased ambient temperature of flash were always smaller than worst case value of 200ms.
Change-Id: Id50636f9ed834ffd7810946798b300e58b2c14d2 Signed-off-by: Uwe Poeche uwe.poeche@siemens.com --- M src/southbridge/intel/common/spi.c 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/34173/4
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34173 )
Change subject: southbridge/intel/common/spi.c: Increase SPI-flash erase timeout ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34173/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34173/4//COMMIT_MSG@17 PS4, Line 17: value is necessary. Please adhere to the 72-char line length limit in commit messages.
https://review.coreboot.org/c/coreboot/+/34173/4/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/34173/4/src/southbridge/intel/commo... PS4, Line 34: #include "drivers/spi/spi_flash_internal.h" Please use <>, as it's not relative to the location of this file.
https://review.coreboot.org/c/coreboot/+/34173/4/src/southbridge/intel/commo... PS4, Line 731: unsigned int timeout = 1000 * SPI_FLASH_PROG_TIMEOUT; Why not SPI_FLASH_SECTOR_ERASE_TIMEOUT? That seems to fit much better by name.
Hello Werner Zeh, Patrick Rudolph, Felix Held, Mario Scheithauer, David Hendricks, Paul Menzel, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34173
to look at the new patch set (#5).
Change subject: sb/intel/common/spi: Increase flash erase timeout ......................................................................
sb/intel/common/spi: Increase flash erase timeout
This patch provides an increased timeout (60ms ->200ms) for SPI HW-sequencing flash erase operations. Without that the erase for MRC cache writing on siemens/mc_bdx1 sometimes goes wrong because the timeout stops waiting for flash cycle completion. It was found during continuous integration. Investigation showed that the used flash type takes sporadic (e.g.5% of the test cycles) more time for completion of erasing operation if the ambient temperature increases. The measured time values are in range of data sheet of SPI flash. 60ms is a typical value. So increasing the value is necessary.
tested on siemens/bdx1; measured time values with increased ambient temperature of flash were always smaller than worst case value of 200ms.
Change-Id: Id50636f9ed834ffd7810946798b300e58b2c14d2 Signed-off-by: Uwe Poeche uwe.poeche@siemens.com --- M src/southbridge/intel/common/spi.c 1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/34173/5
Uwe Poeche has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34173 )
Change subject: sb/intel/common/spi: Increase flash erase timeout ......................................................................
Patch Set 5:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34173/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34173/4//COMMIT_MSG@17 PS4, Line 17: value is necessary.
Please adhere to the 72-char line length limit in commit messages.
Done
https://review.coreboot.org/c/coreboot/+/34173/4/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/34173/4/src/southbridge/intel/commo... PS4, Line 34: #include "drivers/spi/spi_flash_internal.h"
Please use <>, as it's not relative to the location of this file.
Done
https://review.coreboot.org/c/coreboot/+/34173/4/src/southbridge/intel/commo... PS4, Line 731: unsigned int timeout = 1000 * SPI_FLASH_PROG_TIMEOUT;
Why not SPI_FLASH_SECTOR_ERASE_TIMEOUT? That seems to fit much better […]
Done
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34173 )
Change subject: sb/intel/common/spi: Increase flash erase timeout ......................................................................
Patch Set 5:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34173/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34173/5//COMMIT_MSG@9 PS5, Line 9: 200ms it's 1s now
https://review.coreboot.org/c/coreboot/+/34173/5//COMMIT_MSG@15 PS5, Line 15: operation if the ambient temperature increases. The measured time values are in Maybe I'm wrong, but Gerrit shows this line as 7 chars too long.
https://review.coreboot.org/c/coreboot/+/34173/5/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/34173/5/src/southbridge/intel/commo... PS5, Line 733: //unsigned int timeout = 1000 * SPI_FLASH_PROG_TIMEOUT; please drop
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34173 )
Change subject: sb/intel/common/spi: Increase flash erase timeout ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34173/5/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/34173/5/src/southbridge/intel/commo... PS5, Line 31: And once you touch this file you can delete this newline, too
https://review.coreboot.org/c/coreboot/+/34173/5/src/southbridge/intel/commo... PS5, Line 35: Get rid of this extra newline please.
Hello Werner Zeh, Patrick Rudolph, Felix Held, Mario Scheithauer, David Hendricks, Paul Menzel, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34173
to look at the new patch set (#6).
Change subject: sb/intel/common/spi: Increase flash erase timeout ......................................................................
sb/intel/common/spi: Increase flash erase timeout
This patch provides an increased timeout (60ms ->1s) for SPI HW-sequencing flash erase operations. Without that the erase for MRC cache writing on siemens/mc_bdx1 sometimes goes wrong because the timeout stops waiting for flash cycle completion. It was found during continuous integration. Investigation showed that the used flash type takes sporadic (e.g. 5% of the test cycles) more time for completion of erasing operation if the ambient temperature increases. The measured time values are in range of data sheet of SPI flash. 60ms is a typical value. So increasing the value is necessary.
tested on siemens/bdx1; measured time values with increased ambient temperature of flash were always smaller than worst case value of 1s.
Change-Id: Id50636f9ed834ffd7810946798b300e58b2c14d2 Signed-off-by: Uwe Poeche uwe.poeche@siemens.com --- M src/southbridge/intel/common/spi.c 1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/34173/6
Hello Werner Zeh, Patrick Rudolph, Felix Held, Mario Scheithauer, David Hendricks, Paul Menzel, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34173
to look at the new patch set (#7).
Change subject: sb/intel/common/spi: Increase flash erase timeout ......................................................................
sb/intel/common/spi: Increase flash erase timeout
This patch provides an increased timeout (60ms ->1s) for SPI HW-sequencing flash erase operations. Without that the erase for MRC cache writing on siemens/mc_bdx1 sometimes goes wrong because the timeout stops waiting for flash cycle completion. It was found during continuous integration. Investigation showed that the used flash type takes sporadic (e.g. 5% of the test cycles) more time for completion of erasing operation if the ambient temperature increases. The measured time values are in range of data sheet of SPI flash. 60ms is a typical value. So increasing the value is necessary.
tested on siemens/bdx1; measured time values with increased ambient temperature of flash were always smaller than worst case value of 1s.
Change-Id: Id50636f9ed834ffd7810946798b300e58b2c14d2 Signed-off-by: Uwe Poeche uwe.poeche@siemens.com --- M src/southbridge/intel/common/spi.c 1 file changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/34173/7
Uwe Poeche has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34173 )
Change subject: sb/intel/common/spi: Increase flash erase timeout ......................................................................
Patch Set 7:
(5 comments)
https://review.coreboot.org/c/coreboot/+/34173/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34173/5//COMMIT_MSG@9 PS5, Line 9: 200ms
it's 1s now
Done
https://review.coreboot.org/c/coreboot/+/34173/5//COMMIT_MSG@15 PS5, Line 15: operation if the ambient temperature increases. The measured time values are in
Maybe I'm wrong, but Gerrit shows this line as 7 chars too long.
Done
https://review.coreboot.org/c/coreboot/+/34173/5/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/34173/5/src/southbridge/intel/commo... PS5, Line 31:
And once you touch this file you can delete this newline, too
Done
https://review.coreboot.org/c/coreboot/+/34173/5/src/southbridge/intel/commo... PS5, Line 35:
Get rid of this extra newline please.
Done
https://review.coreboot.org/c/coreboot/+/34173/5/src/southbridge/intel/commo... PS5, Line 733: //unsigned int timeout = 1000 * SPI_FLASH_PROG_TIMEOUT;
please drop
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34173 )
Change subject: sb/intel/common/spi: Increase flash erase timeout ......................................................................
Patch Set 7: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/34173/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34173/7//COMMIT_MSG@9 PS7, Line 9: ->1s Space before 1?
Hello Werner Zeh, Patrick Rudolph, Felix Held, Mario Scheithauer, Paul Menzel, David Hendricks, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34173
to look at the new patch set (#8).
Change subject: sb/intel/common/spi: Increase flash erase timeout ......................................................................
sb/intel/common/spi: Increase flash erase timeout
This patch provides an increased timeout (60ms -> 1s) for SPI HW-sequencing flash erase operations. Without that the erase for MRC cache writing on siemens/mc_bdx1 sometimes goes wrong because the timeout stops waiting for flash cycle completion. It was found during continuous integration. Investigation showed that the used flash type takes sporadic (e.g. 5% of the test cycles) more time for completion of erasing operation if the ambient temperature increases. The measured time values are in range of data sheet of SPI flash. 60ms is a typical value. So increasing the value is necessary.
tested on siemens/bdx1; measured time values with increased ambient temperature of flash were always smaller than worst case value of 1s.
Change-Id: Id50636f9ed834ffd7810946798b300e58b2c14d2 Signed-off-by: Uwe Poeche uwe.poeche@siemens.com --- M src/southbridge/intel/common/spi.c 1 file changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/34173/8
Uwe Poeche has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34173 )
Change subject: sb/intel/common/spi: Increase flash erase timeout ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34173/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34173/7//COMMIT_MSG@9 PS7, Line 9: ->1s
Space before 1?
Done
Hello Werner Zeh, Patrick Rudolph, Felix Held, Mario Scheithauer, Paul Menzel, David Hendricks, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34173
to look at the new patch set (#9).
Change subject: sb/intel/common/spi: Increase flash erase timeout ......................................................................
sb/intel/common/spi: Increase flash erase timeout
This patch provides an increased timeout (60ms -> 1s) for SPI HW-sequencing flash erase operations. Without that the erase for MRC cache writing on siemens/mc_bdx1 sometimes goes wrong because the timeout stops waiting for flash cycle completion. It was found during continuous integration. Investigation showed that the used flash type takes sporadic (e.g. 5% of the test cycles) more time for completion of erasing operation if the ambient temperature increases. The measured time values are in range of data sheet of SPI flash. 60ms is a typical value. So increasing the value is necessary.
tested on siemens/bdx1; measured time values with increased ambient temperature of flash were always smaller than worst case value of 1s.
Change-Id: Id50636f9ed834ffd7810946798b300e58b2c14d2 Signed-off-by: Uwe Poeche uwe.poeche@siemens.com --- M src/southbridge/intel/common/spi.c 1 file changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/34173/9
Hello Werner Zeh, Patrick Rudolph, Felix Held, Mario Scheithauer, Paul Menzel, David Hendricks, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34173
to look at the new patch set (#10).
Change subject: sb/intel/common/spi: Increase flash erase timeout ......................................................................
sb/intel/common/spi: Increase flash erase timeout
This patch provides an increased timeout (60ms -> 1s) for SPI HW-sequencing flash erase operations. Without that the erase for MRC cache writing on siemens/mc_bdx1 sometimes goes wrong because the timeout stops waiting for flash cycle completion. It was found during continuous integration. Investigation showed that the used flash type takes sporadic (e.g. 5% of the test cycles) more time for completion of erasing operation if the ambient temperature increases. The measured time values are in range of data sheet of SPI flash. 60ms is a typical value. So increasing the value is necessary.
tested on siemens/bdx1; measured time values with increased ambient temperature of flash were always smaller than worst case value of 1s.
Change-Id: Id50636f9ed834ffd7810946798b300e58b2c14d2 Signed-off-by: Uwe Poeche uwe.poeche@siemens.com --- M src/southbridge/intel/common/spi.c 1 file changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/34173/10
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34173 )
Change subject: sb/intel/common/spi: Increase flash erase timeout ......................................................................
Patch Set 11: Code-Review+2
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34173 )
Change subject: sb/intel/common/spi: Increase flash erase timeout ......................................................................
sb/intel/common/spi: Increase flash erase timeout
This patch provides an increased timeout (60ms -> 1s) for SPI HW-sequencing flash erase operations. Without that the erase for MRC cache writing on siemens/mc_bdx1 sometimes goes wrong because the timeout stops waiting for flash cycle completion. It was found during continuous integration. Investigation showed that the used flash type takes sporadic (e.g. 5% of the test cycles) more time for completion of erasing operation if the ambient temperature increases. The measured time values are in range of data sheet of SPI flash. 60ms is a typical value. So increasing the value is necessary.
tested on siemens/bdx1; measured time values with increased ambient temperature of flash were always smaller than worst case value of 1s.
Change-Id: Id50636f9ed834ffd7810946798b300e58b2c14d2 Signed-off-by: Uwe Poeche uwe.poeche@siemens.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34173 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Werner Zeh werner.zeh@siemens.com --- M src/southbridge/intel/common/spi.c 1 file changed, 1 insertion(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 8430dc8..6fece4f 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -28,7 +28,6 @@ #include <device/device.h> #include <device/pci.h> #include <spi_flash.h> - #include <spi-generic.h>
#include "spi.h" @@ -727,7 +726,7 @@ u32 start, end, erase_size; int ret; uint16_t hsfc; - uint16_t timeout = 1000 * 60; + unsigned int timeout = 1000 * SPI_FLASH_SECTOR_ERASE_TIMEOUT;
erase_size = flash->sector_size; if (offset % erase_size || len % erase_size) {
-
Mario Scheithauer (Code Review) -
Martin Roth (Code Review)
-
Nico Huber (Code Review)
-
Paul Menzel (Code Review)
-
Uwe Poeche (Code Review)
-
Werner Zeh (Code Review)