[S] Change in coreboot[master]: mb/google/nissa/var/craask: Modify DPTF settings

[Reka Norman (Code Review)]

Attention is currently required from: David Wu, Tarun Tuli, Kangheui Won, Ren Kuo, Vidya Gopalakrishnan, Tyler Wang, Eric Lai, Peter Ou.

Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71860 )

Change subject: mb/google/nissa/var/craask: Modify DPTF settings
......................................................................

Patch Set 2:

(3 comments)

File src/mainboard/google/brya/variants/craask/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/71860/comment/02e43388_2c449379 
PS2, Line 112: 	register "power_limits_config[ADL_N_041_6W_CORE]" = "{
             : 		.tdp_pl1_override = 6,
             : 		.tdp_pl2_override = 25,
             : 		.tdp_pl4 = 78,
             : 	}"
             : 
             : 	register "power_limits_config[ADL_N_021_6W_CORE]" = "{
             : 		.tdp_pl1_override = 6,
             : 		.tdp_pl2_override = 25,
             : 		.tdp_pl4 = 78,
             : 	}"
             : 
These are now the same as the defaults in src/soc/intel/alderlake/chipset.cb, so I think we can remove them (in a separate CL).

https://review.coreboot.org/c/coreboot/+/71860/comment/d400f02f_75262769 
PS2, Line 124: 	register "power_limits_config[ADL_N_081_15W_CORE]" = "{
             : 		.tdp_pl1_override = 15,
             : 		.tdp_pl2_override = 35,
             : 		.tdp_pl4 = 83,
             : 	}"
             : 
These are the same as the defaults in src/soc/intel/alderlake/chipset.cb, so I don't think overriding them here makes any difference?

https://review.coreboot.org/c/coreboot/+/71860/comment/b5d49e25_b1e7e8fb 
PS2, Line 156: pl1
Don't you need to change the pl1 / pl2 settings for 15W too?